CS4265 Datasheet, PDF (36/53 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
6.4.5 Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit will select mas-
ter mode, while clearing this bit will select slave mode.
6.5 MCLK Frequency - Address 05h
7
Reserved
6
MCLK
Freq2
5
MCLK
Freq1
4
MCLK
Freq0
3
Reserved
2
Reserved
1
Reserved
0
Reserved
6.5.1 Master Clock Dividers (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK signal. See Table 9 below for the appropriate settings.
Table 9. MCLK Frequency
MCLK Divider
÷1
÷ 1.5
÷2
÷3
÷4
Reserved
Reserved
MCLK Freq2
0
0
0
0
1
1
1
MCLK Freq1
0
0
1
1
0
0
1
MCLK Freq0
0
1
0
1
0
1
x
6.6 Signal Selection - Address 06h
7
SDINSel
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
LOOP
0
Reserved
6.6.1 DAC SDIN Source (Bit 7)
Function:
This bit is used to select the serial audio data source for the DAC as shown in Table 10 below.
Table 10. DAC SDIN Source Selection
SDINSel Setting
0
1
DAC Data Source
SDIN1
SDIN2
6.6.2 Digital Loopback (Bit 1)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer
to “Internal Digital Loopback” on page 26.
6.7 Channel A PGA Control - Address 07h
7
Reserved
6
Reserved
5
Gain5
4
Gain4
3
Gain3
2
Gain2
1
Gain1
0
Gain0
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