CS4265 Datasheet, PDF (20/53 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
SWITCHING CHARACTERISTICS - I²C CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VLC, C_L = 30 pF)
Parameter
Symbol
Min
SCL Clock Frequency
f_scl
-
RESET Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 23) t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of SCL and SDA
(Note 24)
t_rc
-
Fall Time SCL and SDA
(Note 24)
t_fc
-
Setup Time for Stop Condition
t_susp
4.7
Acknowledge Delay from SCL Falling
t_ack
300
Max
100
-
-
-
-
-
-
-
-
1
300
-
1000
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
Notes: 23. Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
24. Guaranteed by design.
RST
SDA
SCL
t _irs
S to p
S tart
t _buf
t _hdst
t
lo w
t _high
R epe ated
S ta rt _{t rd}
t _hdst
t _fc
t
hdd
t _sud
t _ack
t _sust
t _rc
Figure 8. Control Port Timing - I²C Format
S to p
t _fd
t _susp
20
DS657A2