CS4265 Datasheet, PDF (24/53 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the
HPFFreeze bit (see page 35) is set during normal operation, the current value of the DC offset for the each channel
is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible
to perform a system DC offset calibration by:
1) Running the CS4265 with the high pass filter enabled until the filter settles. See the ADC Digital Filter Charac-
teristics section for filter settling time.
2) Disabling the high pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration
point and the CS4265.
4.4 Analog Input Multiplexer, PGA, and Mic Gain
The CS4265 contains a stereo 2-to-1 analog input multiplexer followed by a programmable gain amplifier (PGA).
The input multiplexer is able to select either a line-level input source, or a mic-level input source and route it to the
PGA. The mic-level input passes through a +32 dB gain stage prior to the input multiplexer, allowing it to be used
for microphone level signals without the need for any external gain. The PGA stage provides 12 dB of gain or atten-
uation in 0.5 dB steps. Figure 11 shows the architecture of the input multiplexer, PGA, and mic gain stages.
AINA
MICIN1
AINB
MICIN2
+32 dB
+32 dB
MUX
PGA
Channel A
PGA Gain Bits
Analog Input
Selection Bits
Channel B
PGA Gain Bits
MUX
PGA
Out to ADC
Channel A
Out to ADC
Channel B
Figure 11. Analog Input Architecture
The “Analog Input Selection (Bit 0)” section on page 38 outlines the bit settings necessary to control the input mul-
tiplexer and mic gain. “Channel A PGA Control - Address 07h” on page 36 and “Channel B PGA Control - Address
08h” on page 37 outlines the register settings necessary to control the PGA. By default, the line level input is select-
ed by the input multiplexer, and the PGA is set to 0 dB.
4.5 Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals with-
in the stopband of the filter. However, there is no rejection for input signals which are (n × 6.144 MHz) the digital
passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram for the recommended analog input
circuit that will attenuate noise energy at 6.144 MHz. The use of capacitors which have a large voltage coefficient
(such as general purpose ceramics) must be avoided since these can degrade signal linearity. Any unused analog
input pairs should be left unconnected.
4.5.1 Pseudo-Differential Input
The CS4265 implements a pseudo-differential input stage. The SGND input is intended to be used as a pseudo-
differential reference signal. This feature allows for common mode noise rejection with single-ended signals.
Figure 12 shows a basic diagram outlining the internal implementation of the pseudo-differential input stage. The
Typical Connection Diagram shows the recommended pseudo-differential input topology. If pseudo-differential input
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DS657A2