CS4265 Datasheet, PDF (22/53 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
4. APPLICATIONS
4.1 Recommended Power-Up Sequence
1) Hold RESET low until the power supply, MCLK, and LRCK are stable. In this state, the Control Port is reset to
its default settings.
2) Bring RESET high. The device will remain in a low power state with the PDN bit set by default. The control port
will be accessible.
3) The desired register settings can be loaded while the PDN bit remains set.
4) Clear the PDN bit to initiate the power-up sequence.
4.2 System Clocking
The CS4265 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed
modes as shown in Table 1 below.
Mode
Single Speed
Double Speed
Quad Speed
Sampling Frequency
4-50 kHz
50-100 kHz
100-200 kHz
Table 1. Speed Modes
4.2.1 Master Clock
MCLK/LRCK must maintain an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the frequency
at which audio samples for each channel are clocked into or out of the device. The FM bits (see page 35) and the
MCLK Freq bits (see page 36) configure the device to generate the proper clocks in Master Mode and receive the
proper clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and
LRCK frequencies.
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