CS4265 Datasheet, PDF (17/53 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic ‘0’ = DGND = 0 V;
Logic ‘1’ = VL, C_L = 20 pF) (Note 22)
Parameter
Symbol Min
Typ
Max
Unit
Sample Rate
Single Speed Mode Fs
4
-
50
kHz
Double Speed Mode Fs
50
-
100
kHz
Quad Speed Mode Fs
100
-
200
kHz
MCLK Specifications
MCLK Frequency
fmclk
1.024
-
51.200 MHz
MCLK Input Pulse Width High/Low
tclkhl
8
-
-
ns
MCLK Output Duty Cycle
45
50
55
%
Master Mode
LRCK Duty Cycle
-
50
-
%
SCLK Duty Cycle
-
50
-
%
SCLK falling to LRCK edge
SCLK falling to SDOUT valid
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
Slave Mode
t_slr
-10
-
t_sdo
0
-
t_sdis
16
-
t_sdih
20
-
10
ns
32
ns
-
ns
-
ns
LRCK Duty Cycle
40
50
60
%
SCLK Period
Single Speed Mode ^t_sclkw
------1----0---⁹-------
( 128 ) F s
-
Double Speed Mode ^t_sclkw
(^---6^--1-4^--0-)^---F9----s-
-
-
ns
-
ns
Quad Speed Mode ^t_sclkw
(^---6^--1-4^--0-)^---F9----s-
-
-
ns
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK falling to LRCK edge
SCLK falling to SDOUT valid
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
t_sclkh
30
-
t_sclkl
48
-
t_slr
-10
-
t_sdo
0
-
t_sdis
16
-
t_sdih
20
-
-
ns
-
ns
10
ns
32
ns
-
ns
-
ns
Notes: 22. See figures 3 and 4 on page 18.
DS657A2
17