CS4265 Datasheet, PDF (23/53 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
LRCK
(kHz)
32
44.1
48
64
88.2
96
128
176.4
192
Mode
64x
-
-
-
-
-
-
8.1920
11.2896
12.2880
96x
-
-
-
-
-
-
12.2880
16.9344
18.4320
128x
-
-
-
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
QSM
MCLK (MHz)
192x
256x
384x
512x
-
8.1920 12.2880 16.3840
-
11.2896 16.9344 22.5792
-
12.2880 18.4320 24.5760
12.2880 16.3840 24.5760 32.7680
16.9344 22.5792 33.8680 45.1584
18.4320 24.5760 36.8640 49.1520
24.5760 32.7680
-
-
33.8680 45.1584
-
-
36.8640 49.1520
-
-
DSM
Table 2. Common Clock Frequencies
768x
1024x
24.5760 32.7680
33.8680 45.1584
36.8640 49.1520
-
-
-
-
-
-
-
-
-
-
-
-
SSM
4.2.2 Master Mode
As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from MCLK with
LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 10.
MC LK F re q B its
MC LK
÷1
000
÷1.5
001
÷2
010
÷3
011
÷4
100
÷256
00
÷128
01
÷64
10
F M B its
÷4
00
÷2
01
÷1
10
LRC K
SC LK
Figure 10. Master Mode Clocking
4.2.3 Slave Mode
In Slave mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sample rate,
Fs, and must be synchronously derived from the supplied master clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to 128x, 64x,
48x or 32x Fs depending on the desired speed mode. Refer to Table 3 for required clock ratios.
SCLK/LRCK Ratio
Single Speed
32x, 48x, 64x, 128x
Double Speed
32x, 48x, 64x
Quad Speed
32x, 48x, 64x
Table 3. Slave Mode Serial Bit Clock Ratios
4.3 High Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS4265, a small DC offset may be driven into the
A/D converter. The CS4265 includes a high pass filter after the decimator to remove any DC offset which could result
in recording a DC level, possibly yielding clicks when switching between devices in a multichannel system.
DS657A2
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