CS4340_05 Datasheet, PDF (3/25 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC for Audio

CS4340
5. PARAMETER DEFINITIONS ................................................................................................................21
6. REFERENCES ......................................................................................................................................22
7. PACKAGE DIMENSIONS ....................................................................................................................23
7.1 SOIC ..............................................................................................................................................23
7.2 TSSOP ..........................................................................................................................................24
8. PACKAGE THERMAL RESISTANCE .................................................................................................25
LIST OF FIGURES
Figure 1. Output Test Load ...........................................................................................................................6
Figure 2. Maximum Loading..........................................................................................................................6
Figure 3. Single-Speed Stopband Rejection .................................................................................................9
Figure 4. Single-Speed Transition Band .......................................................................................................9
Figure 5. Single-Speed Transition Band (Detail)...........................................................................................9
Figure 6. Single-Speed Passband Ripple .....................................................................................................9
Figure 7. Double-Speed Stopband Rejection................................................................................................9
Figure 8. Double-Speed Transition Band......................................................................................................9
Figure 9. Double-Speed Transition Band (Detail) .......................................................................................10
Figure 10. Double-Speed Passband Ripple................................................................................................10
Figure 11. Serial Input Timing (External SCLK) ..........................................................................................11
Figure 12. Internal Serial Mode Input Timing ..............................................................................................12
Figure 13. Internal Serial Clock Generation ................................................................................................12
Figure 14. Typical Connection Diagram......................................................................................................15
Figure 15. CS4340 Format 0 - I²S up to 24-Bit Data ..................................................................................17
Figure 16. CS4340 Format 1 - Left Justified up to 24-Bit Data ...................................................................17
Figure 17. CS4340 Format 2 - Right Justified, 24-Bit Data.........................................................................18
Figure 18. CS4340 Format 3 - Right Justified, 16-Bit Data.........................................................................18
Figure 19. De-Emphasis Curve...................................................................................................................18
LIST OF TABLES
Table 1.CS4340 Speed Modes ...................................................................................................................16
Table 2.Single-Speed Mode Standard Frequencies ...................................................................................16
Table 3.Double-Speed Mode Standard Frequencies..................................................................................16
Table 4.Internal SCLK/LRCK Ratio.............................................................................................................17
Table 5.Digital Interface Format - DIF1 and DIF0 .......................................................................................17
Table 6.De-Emphasis Control .....................................................................................................................18
DS297F3
3