CS4340_05 Datasheet, PDF (19/25 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC for Audio

CS4340
4.5 Power-up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supply and configuration pins
are stable, and the clocks are locked to the appropriate frequencies discussed in section 4.2. It is also recommended
that reset be enabled if the analog supply drops below the minimum specified operating voltage to prevent power
glitch related issues.
4.6 Popguard^® Transient Control
The CS4340 uses Popguard^® technology to minimize the effects of output transients during power-up and power-
down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes
the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC
when RST is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-
blocking capacitors.
4.6.1 Power-up
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Fol-
lowing a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent volt-
age. Approximately 10,000 LRCK cycles later, the outputs reach V_Q and audio output begins. This gradual
voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, min-
imizing the power-up transient.
4.6.2 Power-down
To prevent transients at power-down, the device must first enter its power-down state by enabling RST. When
this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR.
In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly dis-
charge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for
the next power-on.
4.6.3 Discharge Time
To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors
have fully discharged before turning on the power or exiting the power-down state. If not, a transient will occur
when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-
down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 µF capacitor, the
minimum power-down time will be approximately 0.4 seconds.
DS297F3
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