CS4340_05 Datasheet, PDF (12/25 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC for Audio

CS4340
SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK
Parameters
Symbol
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate
Single-Speed Mode Fs
Double-Speed Mode Fs
LRCK Duty Cycle
SCLK Period
(Note 7) t_sclkw
SCLK rising to LRCK edge
t_sclkr
SDATA valid to SCLK rising setup time
t_sdlrs
SCLK rising to SDATA hold time
t_sdh
MCLK / LRCK = 512, 256 or 128
Min
1.024
45
4
50
-------1---------
SCLK
Typ
-
-
-
-
(Note 6)
-
-
(^{---5---1----21---})^{---F----s- + 10}
(^{---5---1----21---})^{---F----s- + 15}
t--_{s---c--l--k--w--}
2
-
-
Max
25.6
55
50
100
-
-
-
-
SCLK rising to SDATA hold time
t_sdh
MCLK / LRCK = 384 or 192
----------1----------- + 15
( 384 ) F s
-
-
Notes: 6. The Duty Cycle must be 50% +/− 1/2 MCLK Period.
7. See section 4.2.1 for derived internal frequencies.
LRCK
SDATA
t _sclkr
t _sdlrs t _sdh
t _sclkw
*INTERNAL SCLK
Figure 12. Internal Serial Mode Input Timing
*The SCLK pulses shown are internal to the CS4340.
LRCK
Units
MHz
%
kHz
kHz
%
s
s
ns
ns
ns
MCLK
1
N
N
2
*INTERNAL SCLK
SDATA
Figure 13. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4340. N equals MCLK divided by SCLK
12
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