CS4340_05 Datasheet, PDF (17/25 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC for Audio

CS4340
The internal serial clock is utilized when additional de-emphasis control is required. Operation in the Internal
Serial Clock mode is identical to operation with an external SCLK synchronized with LRCK; however, External
SCLK mode is recommended for system clocking applications.
Input
MCLK/LRCK
Ratio
512, 256, 128
384, 192
512, 256, 128
I²S up to 24
Bits
X
X
-
Digital Interface Format Selection
Left Justified 24 Right Justified Right Justified
Bits
24 Bits
16 Bits
-
-
X
X
X
X
X
X
-
Internal
SCLK/LRCK
Ratio
32
48
64
Table 4. Internal SCLK/LRCK Ratio
4.2.2 External Serial Clock Mode
The device will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the
SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode if no low
to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.
4.3 Digital Interface Format
The device will accept audio samples in several digital interface formats as illustrated in Table 5. The desired format
is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship between LRCK, SCLK and
SDIN, see Figures 15 through 18.
DIF1
0
0
1
1
DIF0
DESCRIPTION
0 I²S, up to 24-bit data
1 Left Justified, up to 24-bit data
0 Right Justified, 24-bit Data
1 Right Justified, 16-bit Data
FORMAT
0
1
2
3
FIGURE
15
16
17
18
Table 5. Digital Interface Format - DIF1 and DIF0
LRCK
SCLK
SDIN
LRCK
SCLK
SDIN
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 15. CS4340 Format 0 - I²S up to 24-Bit Data
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 16. CS4340 Format 1 - Left Justified up to 24-Bit Data
DS297F3
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