CS4340_05 Datasheet, PDF (16/25 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC for Audio

CS4340
4. APPLICATIONS
4.1 Sample Rate Range/Operational Mode
The device operates in one of two operational modes determined by the Master Clock to Left/Right Clock ratio (see
section 4.2). Sample rates outside the specified range for each mode are not supported.
Input Sample Rate (Fs)
4 kHz - 50 kHz
50 kHz - 100 kHz
MODE
Single-Speed Mode
Double-Speed Mode
Table 1. CS4340 Speed Modes
4.2 System Clocking
The device requires external generation of the master (MCLK) and left/right (LRCK) clocks. The device also requires
external generation of the serial clock (SCLK) if the internal serial clock is not used. The LRCK, defined also as the
input sample rate Fs, must be synchronously derived from MCLK according to specified ratios. The specified ratios
of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated
in Tables 2 and 3.
Sample Rate
(kHz)
32
256x
8.1920
MCLK (MHz)
384x
12.2880
512x
16.3840
44.1
11.2896
16.9344
22.5792
48
12.2880
18.4320
24.5760
Table 2. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
64
88.2
96
MCLK (MHz)
128x
192x
8.1920
12.2880
11.2896
16.9344
12.2880
18.4320
Table 3. Double-Speed Mode Standard Frequencies
4.2.1 Internal Serial Clock Mode
The device will enter the Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin
for 2 consecutive periods of LRCK. In this mode, the SCLK is internally derived and synchronous with MCLK
and LRCK. The SCLK/LRCK ratio is either 32, 48, or 64 depending upon the MCLK/LRCK ratio and the Digital
Interface Format selection (see Table 4).
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