CS2100-CP_09 Datasheet, PDF (27/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier

8.3.3
CS2100-CP
Enable Device Configuration Registers 1 (EnDevCfg1)
This bit, in conjunction with EnDevCfg2, configures the device for control port mode. These EnDevCfg
bits can be set in any order and at any time during the control port access sequence, however they must
both be set before normal operation can occur.
EnDevCfg1
0
1
Application:
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 21
Note: EnDevCfg2 must also be set to enable control port mode. See “SPI / I²C Control Port” on
page 21.
8.4 Global Configuration (Address 05h)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Freeze
2
Reserved
1
Reserved
0
EnDevCfg2
8.4.1
Device Configuration Freeze (Freeze)
Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h - 04h)
but keeps them from taking effect until this bit is cleared.
FREEZE
0
1
Device Control and Configuration Registers
Register changes take effect immediately.
Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without
the changes taking effect until after the FREEZE bit is cleared.
8.4.2
Enable Device Configuration Registers 2 (EnDevCfg2)
This bit, in conjunction with EnDevCfg1, configures the device for control port mode. These EnDevCfg
bits can be set in any order and at any time during the control port access sequence, however they must
both be set before normal operation can occur.
EnDevCfg2
0
1
Application:
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 21
Note: EnDevCfg1 must also be set to enable control port mode. See “SPI / I²C Control Port” on
page 21.
8.5 Ratio (Address 06h - 09h)
7
MSB
MSB-8
LSB+15
LSB+7
6
5
4
3
2
1
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
0
MSB-7
MSB-15
LSB+8
LSB
These registers contain the User Defined Ratio as shown in the “Register Quick Reference” section on
page 24. These 4 registers form a single 32-bit ratio value as shown above. See “Output to Input Frequency
Ratio Configuration” on page 17 and “Calculating the User Defined Ratio” on page 30 for more details.
DS840F1
27