CS2100-CP_09 Datasheet, PDF (1/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier

CS2100-CP
Fractional-N Clock Multiplier
Features
 Clock Multiplier / Jitter Reduction
– Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery or Intermittent 50 Hz to 30
MHz Clock Source
 Highly Accurate PLL Multiplication Factor
– Maximum Error Less Than 1 PPM in High-
Resolution Mode
 I²C™ / SPI™ Control Port
 Configurable Auxiliary Output
 Flexible Sourcing of Reference Clock
– External Oscillator or Clock Source
– Supports Inexpensive Local Crystal
 Minimal Board Space Required
– No External Analog Loop-filter
Components
General Description
The CS2100-CP is an extremely versatile system
clocking device that utilizes a programmable phase
lock loop. The CS2100-CP is based on a hybrid ana-
log-digital PLL architecture comprised of a unique
combination of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for generation of a low-jitter clock relative to an exter-
nal noisy synchronization clock at frequencies as low
as 50 Hz. The CS2100-CP supports both I²C and SPI
for full software control.
The CS2100-CP is available in a 10-pin MSOP pack-
age in Commercial (-10°C to +70°C) grade. Customer
development kits are also available for device evalua-
tion. Please see “Ordering Information” on page 32 for
complete details.
I²C/SPI
Software Control
8 MHz to 75 MHz
Low-Jitter Timing
Reference
50 Hz to 30 MHz
Frequency
Reference
I²C / SPI
3.3 V
Timing Reference
Frequency Reference
PLL Output
Lock Indicator
Fractional-N
Frequency Synthesizer
Output to Input
Clock Ratio
N
Digital PLL & Fractional
N Logic
Auxiliary
Output
6 to 75 MHz
PLL Output
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Copyright  Cirrus Logic, Inc. 2009
(All Rights Reserved)
AUG '09
DS840F1