CS2100-CP_09 Datasheet, PDF (19/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier

5.3.3
CS2100-CP
Effective Ratio (R_EFF)
The Effective Ratio (R_EFF) is an internal calculation comprised of R_UD and the appropriate modifiers, as
previously described. R_EFF is calculated as follows:
R_EFF = R_UD • R_MOD
To simplify operation the device handles some of the ratio calculation functions automatically (such as
when the internal timing reference clock divider is set). For this reason, the Effective Ratio does not need
to be altered to account for internal dividers.
Ratio modifiers which would produce an overflow or truncation of R_EFF should not be used; For example
if R_UD is 1024 an R_MOD of 8 would produce an R_EFF value of 8192 which exceeds the 4096 limit of the
12.20 format. In all cases, the maximum and minimum allowable values for R_EFF are dictated by the fre-
quency limits for both the input and output clocks as shown in the “AC Electrical Characteristics” on
page 7.
5.3.4
Ratio Configuration Summary
The R_UD is the user defined ratio stored in the register space. The resolution for the R_UD is selectable by
setting LFRatioCfg. R-Mod is applied if selected. The user defined ratio, and ratio modifier make up the
effective ratio R_EFF, the final calculation used to determine the output to input clock ratio. The effective
ratio is then corrected for the internal dividers. The conceptual diagram in Figure 17 summarizes the fea-
tures involved in the calculation of the ratio values used to generate the fractional-N value which controls
the Frequency Synthesizer.
RefClkDiv[1:0]
Timing Reference Clock
(XTI/REF_CLK)
Effective Ratio REFF
Divide
SysClk
Frequency
Synthesizer
PLL Output
User Defined Ratio RUD
Ratio
Ratio Format
12.20
20.12
RModSel[2:0]
Ratio
Modifier
RefClkDiv[1:0]
R Correction
N
Digital PLL &
Fractional N Logic
LFRatioCfg
Frequency Reference Clock
(CLK_IN)
Figure 17. Ratio Feature Summary
Referenced Control
Register Location
Ratio......................................“Ratio (Address 06h - 09h)” on page 27
LFRatioCfg ............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 29
RModSel[2:0] ........................“R-Mod Selection (RModSel[2:0])” section on page 26
RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 28
DS840F1
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