CS2100-CP_09 Datasheet, PDF (22/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier

CS2100-CP
The control port operates with either the SPI or I²C interface, with the CS2100 acting as a slave device. SPI Mode
is selected if there is a high-to-low transition on the AD0/CS pin after power-up. I²C Mode is selected by connecting
the AD0/CS pin through a resistor to VD or GND, thereby permanently selecting the desired AD0 bit address state.
In both modes the EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation.
WARNING: All “Reserved” registers must maintain their default state to ensure proper functional operation.
Referenced Control
Register Location
EnDevCfg1 ............................“Enable Device Configuration Registers 1 (EnDevCfg1)” on page 27
EnDevCfg2 ............................“Enable Device Configuration Registers 2 (EnDevCfg2)” section on page 27
6.1 SPI Control
In SPI Mode, CS is the chip select signal; CCLK is the control port bit clock (sourced from a microcontroller),
and CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The
device only supports write operations.
Figure 20 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The first
eight bits on CDIN form the chip address and must be 10011110. The next eight bits form the Memory Ad-
dress Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are
the data which will be placed into the register designated by the MAP.
There is MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the
MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will automatically incre-
ment after each byte is read or written, allowing block writes of successive registers.
CS
CCLK
CDIN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CHIP ADDRESS
MAP BYTE
DATA
DATA +n
1 0 0 1 1 1 1 0 INCR 6 5 4 3 2 1 0 7 6
10 7 6
10
Figure 20. Control Port Timing in SPI Mode
6.2 I²C Control
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL.
There is no CS pin. The AD0 pin forms the least-significant bit of the chip address and should be connected
to VD or GND as appropriate. The state of the AD0 pin should be maintained throughout operation of the
device.
The signal timings for a read and write cycle are shown in Figure 21 and Figure 22. A Start condition is de-
fined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the
clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS2100 after
a Start condition consists of the 7-bit chip address field and a R/W bit (high for a read, low for a write). The
upper 6 bits of the 7-bit address field are fixed at 100111 followed by the logic state of the AD0 pin. The
eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Point-
er (MAP) which selects the register to be read or written. If the operation is a read, the contents of the reg-
ister pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or
writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from
the CS2100 after each input byte is read and is input from the microcontroller after each transmitted byte.
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