CS1810XX Datasheet, PDF (26/54 Pages) Cirrus Logic – Digital Audio Networking Processor

CobraNet Hardware User’s Manual
Host Management Interface (HMI)
7.3 Host Port Timing - Intel^® Mode
(C_L = 20 pF)
Parameter
Symbol
Min
Max Unit
Address setup before HCS and HRD low or HCS and HWR
t_ias
low
5
-
ns
Address hold time after HCS and HRD low or HCS and HWR
t_iah
high
5
-
ns
Read
Delay between HRD then HCS low or HCS then HRD low
t_icdr
0
-
ns
Data valid after HCS and HRD low
t_idd
-
18
ns
HCS and HRD low for read
t_irpw
24
-
ns
Data hold time after HCS or HRD high
t_idhr
8
-
ns
Data high-Z after HCS or HRD high
t_idis
-
18
ns
HCS or HRD high to HCS and HRD low for next read
t_ird
30
-
ns
HCS or HRD high to HCS and HWR low for next write
t_irdtw
30
-
ns
HRD rising to HREQ rising
t_irdirqhl
-
12
ns
Write
Delay between HWR then HCS low or HCS then HWR low
t_icdw
0
-
ns
Data setup before HCS or HWR high
t_idsu
8
-
ns
HCS and HWR low for write
t_iwpw
24
-
ns
Data hold after HCS or HWR high
t_idhw
8
-
ns
HCS or HWR high to HCS and HRD low for next read
t_iwtrd
30
-
ns
HCS or HWR high to HCS and HWR low for next write
t_iwd
30
-
ns
HWR rising to HREQ falling
t_iwrbsyl
-
12
ns
NOTES:1. The system designer should be aware that the actual maximum speed of the communication port may
be limited by the firmware application. Hardware handshaking on the HREQ pin/bit should be observed
to prevent overflowing the input data buffer.
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©Copyright 2005 Cirrus Logic, Inc.
DS651UM23
Version 2.3