CS1810XX Datasheet, PDF (17/54 Pages) Cirrus Logic – Digital Audio Networking Processor

CobraNet Hardware User’s Manual
Synchronization
5.0 Synchronization
Figure 3 shows clock related circuits for the CS1810xx/CS4961xx and board design
(CM-2). This circuitry allows the synchronization modes documented below to be
achieved. Modes are distinguished by different settings of the multiplexors and software
elements.
DAC
VCXO
24.576 MHz
MCLK_IN
MCLK_SEL
RefClkEnable
RefClkPolarity
REFCLK_IN
BeatReceived
Edge
Detect
AClkConfig
Sample
Phase
Counter
MCLK_OUT
CS1810xx/CS4961xx
Audio
Clock
Generator
FS1
SLCK
Phase
Detector
Loop
Filter
Legend:
External
Hardware
Component
(CM2)
Internal
Hardware
Component
(CS1810xx, CS4961xx)
Software
Component
Figure 3. Audio Clock Sub-system
5.1 Synchronization Modes
Clock synchronization mode for conductor and performer roles is independently
selectable via management interface variables syncConductorClock and
syncPerformerClock. The role (conductor or performer) is determined by the network
environment including the conductor priority setting of the device and the other devices on
the network. It is possible to ensure you will never assume the conductor role by selecting
a conductor priority of zero. However, it is not reasonable to assume that by setting a high
conductor priority, you will always assume the conductor role. For more information, refer
to CobraNet Programmer’s Reference Manual.
DS651UM23
©Copyright 2005 Cirrus Logic, Inc.
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Version 2.3