CAT34RC02_05 Datasheet, PDF (8/14 Pages) Catalyst Semiconductor – 2-kb I2C Serial EEPROM, Serial Presence Detect

CAT34RC02
address counter can be ‘initialized’ by performing a Sequential Read
‘dummy’ WRITE operation (Fig. 12). The START
condition is followed by the Slave address (with the R/W
bit set to ‘0’) and the desired byte address. Instead of
following up with data, the Master then issues a 2^nd
START, followed by the ‘Immediate Address Read’
sequence, as described earlier.
If the Master acknowledges the 1^st data byte transmitted
by the CAT34RC02, then the device will continue
transmitting as long as each data byte is acknowledged
by the Master (Fig. 13). If the end of memory is reached
during sequential READ, the address counter will ‘wrap-
around’ to the beginning of memory, etc. Sequential
READ works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting
Figure 9. Memory Array
t _FFH
byte address.
ar _{Hardware Write Protectable}
(by connecting WP pin to
P 7FH
Vcc)
Software Write Protectable
(by setting the write
d _{protect flags)}
e ^00H
u _{Figure 10. Software Write Protect (Write)}
tin ^S
T
BUS ACTIVITY: ^A
MASTER ^R
T
on ^{SDALINE S}
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
DATA
O
P
XXXXXXXX XXXXXXXX P
A
A
A
C
C
C
K
K
K
X = Don't Care
c _{* For PSWP A0 is at normal CMOS levels and for RSWP, A0 is at VHV which must be held high beyond the end}
Dis ^{of the STOP condition (approximately 1µs of “overlap” is sufficient).}
Doc. No. 1052, Rev. O
8
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice