CAT34RC02_05 Datasheet, PDF (4/14 Pages) Catalyst Semiconductor – 2-kb I2C Serial EEPROM, Serial Presence Detect

CAT34RC02
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The CAT34RC02 supports the I²C (2-wire) Bus data SCL: Serial Clock
transmission protocol. This Inter-Integrated Circuit Bus The serial clock input pin is used to clock all data
protocol defines any device that sends data to the bus to transfers into or out of the device.
be a transmitter and any device receiving data to be a
receiver. Data transfer is controlled by the Master device
SDA: Serial Data/Address
which generates the serial clock and all START and
STOP conditions for bus access. The CAT34RC02
operates as a Slave device. Both the Master and Slave
The bidirectional serial data/address pin is used to
transfer data into and out of the device. This pin is an
open drain output in transmit mode.
devices can operate as either transmitter or receiver, but
the Master alone assigns those roles. A maximum of 8
devices may be connected to the bus as determined by
art ^{the device address inputs A0, A1, and A2.}
A₀, A₁, A₂: Device Address Inputs
These inputs set the device address. When left floating,
the address pins are internally pulled to ground.
WP: Write Protect
This input, when grounded or left floating, allows write
operations to the entire memory. When this pin is tied to
VCC, the entire memory is write protected.
P Figure 1. Bus Timing
tF
d _SCL
e ^tSU:STA
u ^{SDA IN}
tin ^{SDA OUT}
tHIGH
tR
tLOW
tLOW
tHD:DAT
tHD:STA
tSU:DAT
tAA
tDH
tSU:STO
tBUF
Figure 2. Write Cycle Timing
n _SCL
Disco ^SDA
8th Bit
Byte n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 1052, Rev. O
4
STOP BIT
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice