CAT34RC02_05 Datasheet, PDF (6/14 Pages) Catalyst Semiconductor – 2-kb I2C Serial EEPROM, Serial Presence Detect

CAT34RC02
WRITE OPERATIONS
Byte Write
acknowledge the Slave address, as long as internal
write is in progress.
In Byte Write mode the Master creates a START condition, WRITE PROTECTION
and then broadcasts the Slave address, byte address
and data to be written. The Slave acknowledges the Hardware Write Protection
three bytes by pulling down the SDA line during the 9^th
clock cycle following each byte. The Master creates a
With the WP pin held HIGH, the entire memory, as well
STOP condition after the last ACK from the Slave, which
as the SWP flags are protected against WRITE operations
then starts the internal write operation (Fig. 6). During
(Fig. 9). If the WP pin is left floating or is grounded. then
internal write, the Slave will ignore any read/write request
from the Master.
Page Write
t _{The CAT34RC02 contains 256 bytes of data, arranged}
r _{in 16 pages of 16 bytes each. The page is selected by the}
four most significant bits of the address byte presented
a to the device after the Slave address, while the four least
significant bits point to the byte within the page. By
‘loading’ more than one data byte into the device, up to
P _{an entire page can be written in one write cycle (Fig. 7).}
The internal byte address counter will increment after
each data byte. If the Master transmits more than 16
d data bytes, then earlier bytes will be overwritten by later
bytes in a ‘wrap-around’ fashion within the selected
e ^{page. The internal write cycle is started following the}
STOP condition created by the Master.
u _{Acknowledge Polling}
Acknowledge polling can be used to determine if the
tin ^{CAT34RC02 is busy writing or is ready to accept}
commands. Polling is implemented by sending a
‘Selective Read’ command (described under READ
OPERATIONS) to the device. The CAT34RC02 will not
it has no impact on the operation of the CAT34RC02.
Software Write Protection
The lower half of memory (first 128 bytes) can be
protected against WRITE operations by setting one of
two Software Write Protection (SWP) flags/switches.
The PSWP (Permanent Software Write Protection) flag
can be set but not cleared by the user. The RSWP
(Reversible Software Write Protection) flag can be set
and cleared by the user. Whereas the PSWP flag can be
set ‘in-system’, the RSWP flag is meant to be used
during testing. RSWP commands require the presence
of a very high voltage (higher than VCC) on address pin
A0 and fixed logic levels for the other two address pins.
The CAT34RC02 is shipped ‘unprotected’. The state of
the SWP flags can be read by issuing an ‘Immediate
Address Read’ command, with the Slave address
‘preamble’ set to 0110 (6h) instead of the ‘normal’ 1010
(Ah). A SWP READ will return the complemented versions
of the two flags in the last two slots of the resulting data
byte; the other six more significant bits in the data byte
have no meaning to the user (Fig. 11).
n _{Figure 6. Byte Write Timing}
S
oT
BUS ACTIVITY: ^A
MASTER ^R
c^T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
DATA
O
P
SDA LINE S
P
is ^A
A
A
C
C
C
K
K
K
D ^{Figure 7. Page Write Timing}
S
T
BUS ACTIVITY: ^A
SLAVE
MASTER ^R ADDRESS
T
BYTE
ADDRESS (n)
DATA n
DATA n+1
S
T
DATA n+P ^O
P
SDA LINE S
*
P
A
A
A
A
A
C
C
C
C
C
K
K
K
K
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1052, Rev. O
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice