CAT34RC02_05 Datasheet, PDF (7/14 Pages) Catalyst Semiconductor – 2-kb I2C Serial EEPROM, Serial Presence Detect

CAT34RC02
The PSWP flag can be set (forever) by issuing a ‘Byte command attempts to ‘reaffirm’ one of the two switches,
Write’ command, with the Slave address preamble set to then the CAT34RC02 will not acknowledge the command
‘6h’, followed by a ‘don’t care’ address, followed by ‘don’t itself. In addition, the CAT34RC02 will not acknowledge
care’ data and a STOP condition. The CAT34RC02 will a ‘reaffirming’ SWP command, even if the WP pin is
acknowledge the Slave address, dummy byte address LOW.
and dummy data (Fig. 10). The PSWP flag will be
permanently set (after the internal write cycle is
Power-On Reset (POR)
completed).
The CAT34RC02 incorporates Power-On Reset (POR)
circuitry which protects the device against malfunctioning
The SWP commands are shown in Table 1.
while VCC is lower than the recommended operating
Table 1. SWP Commands
t Slave Address
r _Command
a _SWP
READ
RSWP SET
P _RSWP
CLEAR
PSWP SET
PIN
A2 A1 A0
Preamble
Device Address R/W
B7 B6 B5 B4 B3 B2 B1 B0
A2 A1 A0 0
1 1 0 A2 A1 A0
1
0 0 VHV 0
1 10
0
0
1
0
0
1 VHV 0
1 10
0
11
0
A2 A1 A0 0
1 1 0 A2 A1 A0
0
d _{The CAT34RC02 will not acknowledge RSWP or PSWP}
e _{commands, once the PSWP flag is set. If the PSWP flag}
is not set, but the WP pin is HIGH, then the CAT34RC02
u _{will react to RSWP or PSWP commands as follows: if the}
command attempts to ‘flip’ one of the two SWP switches,
tin ^{then the CAT34RC02 will respond the same way the}
regular memory would, i.e. the command and address
(in this case dummy) are acknowledged, but the data (in
this case dummy) will not be acknowledged; if the
voltage.
The device will power up into a read-only state and will
power-down into a reset state when V_CC crosses the
POR level of ~1.3V.
READ OPERATIONS
Immediate Address Read
In standby mode, the CAT34RC02 internal address
counter points to the data byte immediately following the
last byte accessed by a previous operation. If the
‘previous’ byte was the last byte in memory, then the
address counter will point to the first memory byte, etc.
If the CAT34RC02 decodes a Slave address with a ‘1’ in
the R/W bit position (Fig. 8), it will issue an ACK in the 9^th
clock cycle, and will then transmit the data byte being
pointed at by the address counter. The Master can then
stop further transmission by issuing a NoACK, followed
by a STOP condition.
Selective Read
The READ operation can also be started at an address
different from the one stored in the address counter. The
n _{Figure 8. Immediate Address Read Timing}
S
o_T
S
BUS ACTIVITY: ^A
SLAVE
T
MASTER ^R ADDRESS
O
cT
P
SDA LINE S
P
is ^A
N
C
DATA
O
K
A
D^C
K
SCL
8
9
SDA
8th Bit
DATA OUT
NO ACK
STOP
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc No. 1052, Rev. O