CAT34RC02_05 Datasheet, PDF (5/14 Pages) Catalyst Semiconductor – 2-kb I2C Serial EEPROM, Serial Presence Detect

CAT34RC02
I²C BUS PROTOCOL
Device Addressing
The I²C bus consists of two ‘wires’, SCL and SDA. The ^{The Master initiates a data transfer by creating a START}
two ‘wires’ are connected to the supply (VCC) via pull-up
resistors. Master and Slave devices connect to the bus
condition on the bus. The Master then broadcasts an 8-
bit serial Slave address. The four most significant bits of
via their respective SCL and SDA pins. The transmitting ^{the Slave address (the ‘preamble’) are fixed to 1010}
device pulls down the SDA line to ‘transmit’ a ‘0’ and ^{(Ah), for normal read/write operations and 0110 (6h) for}
releases it to ‘transmit’ a ‘1’.
Software Write Protect (SWP) operations (Fig. 5). The
next three bits, A2, A1 and A0, select one of eight possible
(1) Data transfer may be initiated only when the bus is _{Slave devices. The last bit, R/W, specifies whether a}
not busy (see A.C. Characteristics).
(2) During a data transfer, the data line must remain
stable whenever the SCL line is high. An SDA
transition while SCL is high will be interpreted as a
t _{START or STOP condition.}
r _{START Condition}
a The START Condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START condition acts as a ‘wake-up’ call for the
P _{Slave devices. A Slave will not respond to commands}
unless the MASTER generates a START condition.
STOP Condition
d _{The STOP condition completes all commands. It consists}
e ^{of a LOW to HIGH transition on SDA while SCL is HIGH.}
The STOP condition starts the internal write cycle, when
following a WRITE command and sends the Slave into
u _{standby mode, when following a READ command.}
Read (1) or Write (0) operation is to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9^th clock cycle. The Slave will aslo
acknowledge the 8-bit byte address and every data byte
presented in WRITE mode. In READ mode the Slave
shifts out eight bits of data, and then ‘releases’ the SDA
line durng the 9^th clock cycle. If the Master acknowledges
in the 9^th clock cycle (by pulling down the SDA line), then
the Slave continues transmitting. When data transfer is
complete, the Master responds with a NoACK (it does
not acknowledge the last data byte) and the Slave stops
transmitting and waits for a STOP condition.
tin ^{Figure 4. Acknowledge Timing}
SCL FROM
1
MASTER
on ^{DATA OUTPUT}
FROM TRANSMITTER
c_{DATA OUTPUT}
FROM RECEIVER
is START
D^{Figure 5. Slave Address Bits}
8
9
ACKNOWLEDGE
1 0 1 0 A2 A1 A0 R/W Normal Read and Write
DEVICE ADDRESS
0
1
1
0
A2
A1
A0
R/W
Programming the Write
Protect Register
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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Doc No. 1052, Rev. O