CAT28LV65_05 Datasheet, PDF (8/12 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL EEPROM

CAT28LV65
DATA Polling
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O₇ (I/O₀–I/O₆
are indeterminate) until the programming cycle is com-
plete. Upon completion of the self-timed write cycle, all
I/O’s will output true data during a read cycle.
Toggle Bit
In addition to the DATA Polling feature, the device offers
an additional method for determining the completion of
a write cycle. While a write cycle is in progress, reading
data from the device will result in I/O₆ toggling between
one and zero. However, once the write is complete, I/O₆
stops toggling and valid data can be read from the
device.
Ready/BUSY (RDY/BUSY)
The RDY/BUSY pin is an open drain output which
indicates device status during programming. It is pulled
low during the write cycle and released at the end of
programming. Several devices may be OR-tied to the
same RDY/BUSY line.
Figure 7. DATA Polling
ADDRESS
CE
WE
OE
I/O7
Figure 8. Toggle Bit
WE
tOEH
DIN = X
tOE
tWC
DOUT = X
CE
tOEH
tOE
OE
I/O6
(1)
Note:
(1) Beginning and ending state of I/O₆ is indeterminate.
Doc. No. 1024, Rev. D
tWC
8
tOES
DOUT = X
28LV65 F11
tOES
(1)