CAT28LV65_05 Datasheet, PDF (3/12 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL EEPROM

CAT28LV65
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground⁽²⁾ ........... –2.0V to +V_CC + 2.0V
V_CC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current⁽³⁾ ........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
N_END(1)
T_DR(1)
V_ZAP(1)
I_LTH(1)(4)
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
10⁵
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
MODE SELECTION
Mode
CE
WE
OE
I/O
Power
Read
L
H
L
DOUT
ACTIVE
Byte Write (WE Controlled)
L
H
DIN
ACTIVE
Byte Write (CE Controlled)
L
H
DIN
ACTIVE
Standby, and Write Inhibit
H
X
X
High-Z
STANDBY
Read and Write Inhibit
X
H
H
High-Z
ACTIVE
CAPACITANCE T_A = 25°C, f = 1.0 MHz
Symbol
Test
CI/O(1)
Input/Output Capacitance
CIN(1)
Input Capacitance
Max.
10
6
Units
pF
pF
Conditions
VI/O = 0V
VIN = 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V_CC +0.5V, which may overshoot to V_CC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V_CC +1V.
3
Doc. No. 1024, Rev. D