CAT28LV65_05 Datasheet, PDF (7/12 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL EEPROM

CAT28LV65
Page Write
The page write mode of the CAT28LV65 (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes
of data to be programmed within a single EEPROM write
cycle. This effectively reduces the byte-write time by a
factor of 32.
Following an initial WRITE operation (WE pulsed low, for
t_WP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a 32 byte temporary buffer. The page
address where data is to be written, specified by bits A₅
to A₁₂, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A₀ to A₄
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within t_{BLC MAX} of the rising edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within t_{BLC MAX}.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal auto-
matic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
which writes new data back into the cell. A page write will
only write data to the locations that were addressed and
will not rewrite the entire page.
Figure 5. Byte Write Cycle [CE Controlled]
tWC
ADDRESS
tAS
CE
tAH
tCW
tBLC
tOEH
OE
tOES
tCS
tCH
WE
tRB
HIGH-Z
RDY/BUSY
HIGH-Z
DATA OUT
HIGH-Z
DATA IN
Figure 6. Page Mode Write Cycle
OE
DATA VALID
tDS
tDH
CE
tWP
tBLC
WE
ADDRESS
I/O
BYTE 0 BYTE 1
BYTE 2
7
BYTE n BYTE n+1
tWC
LAST BYTE
BYTE n+2
Doc. No. 1024, Rev. D