CAT28LV65_05 Datasheet, PDF (10/12 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL EEPROM

CAT28LV65
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
write timing specifications (Figure 11). Once this is done,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transi-
tions. This gives the user added inadvertent write pro-
tection on power-up in addition to the hardware protec-
tion provided.
To allow the user the ability to program the device with
an EEPROM programmer (or for testing purposes) there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
DATA
ADDRESS
AA
1555
55
0AAA
CE
WE
A0
1555
tWP
tBLC
tWC
BYTE OR
PAGE
WRITES
ENABLED
Figure 12. Resetting Software Data Protection Timing
DATA
ADDRESS
CE
AA
1555
55
0AAA
80
1555
AA
1555
WE
55
0AAA
20 ^tWC
1555
SDP
RESET
DEVICE
UNPROTECTED
Doc. No. 1024, Rev. D
10