CM1231 Datasheet, PDF (4/11 Pages) California Micro Devices Corp – Two-Channel PicoGuard XPTM ESD Clamp Protection Array

Issue X-1
CM1231
CM1231 Inductor Elements
In the CM1231 dual stage PicoGuard XP^TM
architecture, the inductor elements and ESD protection
diodes interact differently compared to the single stage
model.
In the single stage model, the inductive element
presents high impedance at high frequency, i.e. during
an ESD strike. The impedance increases the
resistance of the conduction path leading to the ESD
protection element. This limits the speed that the ESD
pulse can discharge through the single stage
protection element.
In the PicoGuard XP^TM architecture, the inductance
elements are in series to the conduction path leading
to the protected device. The elements actually help to
limit the current and voltage striking the protected
device.
The reactance of the series and the inductor elements
in the second stage forces more of the ESD strike
current to be shunted through the first stage. At the
same time the voltage drop across series element
helps to lower the clamping voltage at the protected
terminal.
The inductor elements also tune the impedance of the
stage by cancelling the capacitive load presented by
the ESD diodes to the signal line. This improves the
signal integrity and makes the ESD protection stages
more transparent to the high bandwidth data signals
passing through the channel.
The innovative PicoGuard XP architecture turns the
disadvantages of the parasitic inductive elements into
useful components that help to limit the ESD current
strike to the protected device and also improves the
signal integrity of the system by balancing the
capacitive loading effects of the ESD diodes.
Graphical Comparison and Test Setup
The following graphs (see Figure 6, Figure 7, and Figure 8) show that the CM1231 (dual stage ESD protector) low-
ers the peak voltage and clamping voltage by 40% across a wide range of loading conditions in comparison to a
standard single stage device. This data was derived using the test setups shown in Figure 9 and Figure 10.
1
0.8
0.6
0.4
0.2
0
0
Normalized Vpeak
5
10
15
20
25
RDUP (Ω)
Single Stage ESD
Device
CM1231
Figure 6. IEC 61000-4-2 Vpeak vs.
Loading (RDUP*)
Normalized Vclamp Initial (0-50ns)
1
0.8
0.6
Single Stage ESD
Device
0.4
CM1231
0.2
0
0
5
10
15
20
25
RDUP (Ω)
Figure 7. IEC 61000-4-2 Vclamp vs.
Loading (RDUP*)
* RDUP indicates the amount of Resistance (load) supplied to the Device Under Protection (DUP) through a vari-
able resistor.
© 2007 California Micro Devices Corp. All rights reserved.
4
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