CM1231 Datasheet, PDF (2/11 Pages) California Micro Devices Corp – Two-Channel PicoGuard XPTM ESD Clamp Protection Array

Issue X-1
CM1231
Single and Dual Clamp ESD Protec-
tion
The following sections describe the standard single
clamp ESD protection device and the dual clamp ESD
protection architecture of the CM1231.
Single Clamp ESD Protection
Conceptually, an ESD protection device performs the
following actions upon a strike of ESD discharge into
the protected ASIC (see Figure 1).
1. When an ESD potential is applied to the system
under test (contact or air-discharge), Kirchoff’s
Current Law (KCL) dictates that the Electrical
Overstress (EOS) currents will immediately divide
throughout the circuit, based on the dynamic
impedance of each path.
2. Ideally, the classic shunt ESD clamp will switch
within 1ns to a low-impedance path and return the
majority of the EOS current to the chassis shield/
reference ground. In actuality, if the ESD compo-
nent's response time (t_CLAMP) is slower than the
ASIC it is protecting, or if the Dynamic Resistance
(R_DYN) is not significantly lower than the ASIC's I/O
cell circuitry, then the ASIC will have to absorb a
large amount of the EOS energy, and may be more
likely to fail.
3. Subsequent to the ESD/EOS event, both devices
must immediately return to their original specifica-
tions, ready for an additional strike. Any deteriora-
tion in parasitics or clamping capability should be
considered a failure, as it can affect signal integrity
or subsequent protection capability (this is known
as "multi-strike" capability.)
ESD Strike
I /O
Connector
ISHUNT
ESDESD
PROTPrEoCteTctIioOnN
DEVIDCeEvice
ASIC
IRESIDUAL
Figure 1. Single Clamp ESD Protection Block Diagram
Dual Clamp ESD Protection
In the CM1231 dual clamp PicoGuard XP^TM
architecture, the first stage begins clamping
immediately, as it does in the single clamp case. The
dramatically reduced I_RES current from stage one
passes through the 1Ω series element and then
gradually feeds into the stage two ESD device (see
Figure 2). The series inductive and resistive elements
further limit the current into the second stage, and
greatly attenuate the resultant peak incident pulse
presented at the ASIC side of the device.
This disconnection between the outside node and the
inside ASIC node allows the stage one clamps to turn
on and remain in the shunt mode before the ASIC
begins to shunt the reduced residual pulse. This gives
the advantage to the ESD component in the current
division equation, and dramatically reduces the
residual energy that the ASIC must dissipate.
I/O
Connector
ESD Strike
1Ω
ESD
Protection
Stage 1
ESD
Protection
Stage 2
ASICASIC
DUT
I _SHUNT1
I _SHUNT2
I _RESIDUAL
Figure 2. Dual Clamp ESD Protection Block
Diagram
© 2007 California Micro Devices Corp. All rights reserved.
2
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