CL-PS7500FE Datasheet, PDF (89/251 Pages) Cirrus Logic – System-on-a Chip for Internet Appliance

CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.15 FIQMSK (0x38) — FIQ Interrupts Mask
76543210
1F0S00 I D
1
F
S
I
D
Write
Read
Reset
always active
nINT8, active-low
nINT6, active-low
INT5, active-high
INT9, active-high
set mask for each interrupt source:
0
do not form part of nFIQ
1
form part of nFIQ
value set by write
set all ‘0’ (none affect nFIQ)
10.3.16 CLKCTL (0x3C) — Clock Control
76543210
XXXXXFM I
On system power up, the clock control register is reset so that all three main clocks have a Divide-by-2
prescale at the inputs to the chip. This register sometimes needs to be reprogrammed as part of the initial
tasks of the operating system, to set the prescalars into Divide-by-1 mode.
Divide-by-2 mode allows faster oscillators to be used with less rigorous mark-space requirements.
F
FCLK divide control
M
MEMRFCK divide control
I
I/O clock divide control
Write
bit[2]
0
1
FCLK × 2 = CPUCLK
FCLK = CPUCLK
bit[1]
0
1
MEMRFCK × 2 = MEMCLK
MEMRFCK = MEMCLK
bit[0]
0
1
IOCK32 × 2 = I_OCLK
IOCK32 = I_OCLK
Read
return above value
Power On Reset only
set all to ‘0’, that is, the Divide-by-2 clocks
Push button reset does not affect this register
88
MEMORY AND I/O PROGRAMMERS’ MODEL
ADVANCE DATA BOOK v2.0
June 1997