CL-PS7500FE Datasheet, PDF (233/251 Pages) Cirrus Logic – System-on-a Chip for Internet Appliance

CL-PS7500FE
System-on-a-Chip for Internet Appliance
Appendix C
C.Using ASTCR at High MEMCLK Frequencies
1. Using ASTCR
Whenever the ARM processor performs a memory cycle, it is clocked by MCLK derived from MEMCLK.
The I/O controller inside CL-PS7500FE is clocked by derivatives of I_OCLK. Thus, when the ARM pro-
cessor performs a read from or a write to an area of I/O space, some synchronization must occur.
The CL-PS7500FE bus controller decodes the address of the ARM processor access and, if it recognizes
it as an I/O access, must send an I/O cycle request signal to the I/O controller. This is synchronized to the
internal I/O clock, IOCK32. The I/O controller then performs the necessary cycle, asserting one (or more)
of the I/O chip select signals, (for example, nCCS).
When the I/O controller can determine that the I/O cycle is about to finish, it asserts an I/O grant signal
synchronized back to the internal memory clock, MEMRFCK. The bus controller then terminates the cycle
by creating a falling edge on MCLK that clocks the ARM processor.
The address from the ARM processor is latched when MCLK is low so that it is held stable throughout I/O
cycles (as well as ROM). It is important that MCLK does not fall too quickly after the end of the I/O chip
select. This could cause the address to change too quickly, violating the required hold time. The
CL-PS7500FE is designed to support an MEMCLK running at a frequency much higher than I_OCLK.
The I/O grant generated by the I/O controller is synchronized quickly back to MEMRFCK and the address
changes sooner after the end of the I/O chip select. To ensure the address hold time is maintained, the
I/O controller must delay the point where it generates the I/O grant.
Using ASTCR, bit 0x032000CC allows the address hold time to be maintained when the MEMCLK fre-
quency is greater than the I_OCLK frequency, at the same time not imposing greater-than-necessary wait
states when MEMCLK is the same, or lower frequency than I_OCLK.
For a given system, fix the I_OCLK frequency at 32 MHz, while the MEMCLK frequency is fixed according
to the speed of DRAM used. The amount of hold time required between the end of the I/O chip select and
the latched address change is determined, then ASTCR is set based on the following details.
232
June 1997
ADVANCE DATA BOOK v2.0