CL-PS7500FE Datasheet, PDF (58/251 Pages) Cirrus Logic – System-on-a Chip for Internet Appliance

CL-PS7500FE
System-on-a-Chip for Internet Appliance
7.3.1.2 Mode Bits
Bits M[4:0] are the mode bits that determine the processor operating mode. The interpretation of the mode
bits is shown in Table 7-1. Not all combinations of the mode bits define a valid processor mode. Only those
explicitly described are used.
Table 7-1. Mode Bits
M[4:0]
10000
10001
10010
10011
10111
11011
Mode
User
FIQ
IRQ
Supervisor
Abort
Undefined
Accessible Register Set
PC, R14–R0
PC, R14_fiq–R8_fiq, R7–R0
PC, R14_irq–R13_irq, R12–R0
PC, R14_svc–R13_svc, R12–R0
PC, R14_abt–R13_abt, R12–R0
PC, R14_und–R13_und, R12–R0
CPSR
CPSR, SPSR_fiq
CPSR, SPSR_irq
CPSR, SPSR_svc
CPSR, SPSR_abt
CPSR, SPSR_und
7.3.1.3 Control Bits
The bottom 28 bits of a PSR (incorporating I, F, and M[4:0]) are known collectively as the control bits. The
control bits change when an exception arises and, in addition, can be manipulated by software when the
processor is in a privileged mode. Unused bits in the PSRs are reserved and their state must be preserved
when changing the flag or control bits. Programs must not rely on specific values from the reserved bits
when checking the PSR status, since they can read as ‘1’ or ‘0’ in future processors.
7.4 Exceptions
Exceptions arise whenever there is a need to break the normal flow of program execution. For example,
the processor can be diverted to handle an interrupt from a peripheral. The processor state just prior to
handling the exception must be preserved so that the original program can be resumed when the excep-
tion routine is complete. Many exceptions can arise at the same time.
The ARM processor handles exceptions by making use of the banked registers to save state. The old PC
and CPSR contents are copied into the appropriate R14 and SPSR, and the PC and mode bits in the
CPSR bits are forced to a value that depends on the exception. Interrupt disable flags are set where
required to prevent otherwise unmanageable nestings of exceptions. In the case of a re-entrant interrupt
handler, R14 and the SPSR should be saved onto a stack in main memory before re-enabling the inter-
rupt.
NOTE: When transferring the SPSR to and from a stack, it is important to transfer the whole 32-bit value, and not
just the flag or control fields.
When simultaneous multiple exceptions arise, a fixed priority determines their order. The priorities are
listed in Section 7.4.7 on page 61.
7.4.1 FIQ
The FIQ (Fast Interrupt reQuest) exception is generated by the interrupt handler within the CL-PS7500FE.
This input is delayed by one clock cycle for synchronization before it can affect the processor execution
flow. It is designed to support a data transfer or channel process, and has sufficient private registers to
June 1997
ADVANCE DATA BOOK v2.0
57
REGISTER DESCRIPTIONS