CL-PS7500FE Datasheet, PDF (36/251 Pages) Cirrus Logic – System-on-a Chip for Internet Appliance

CL-PS7500FE
System-on-a-Chip for Internet Appliance
5. IDC
ARM processor contains a 4-Kbyte mixed-instruction and data cache. The IDC has 256 lines of 16 bytes
(4 words), organized as a four-way set associative cache, and uses the virtual addresses generated by
the processor core. The IDC is always reloaded one line at a time (four words). It can be enabled or dis-
abled through the ARM processor Control register and is disabled on nRESET.
The operation of the cache is further controlled by the cacheable or C bit stored in the Memory Manage-
ment Page table (see the Section 6 on page 38). For this reason, to use the IDC the MMU must be
enabled. However, the two functions can be enabled simultaneously with a single write to the Control reg-
ister.
5.1 Cacheable Bit
The C bit determines whether data being read can be placed in the IDC and used for subsequent read
operations. Typically, main memory is marked as cacheable to improve system performance, and I/O
space as non-cacheable to stop the data being stored in the cache of the CL-PS7500FE. (For example,
if the processor is polling a hardware flag in I/O space, it is important that the processor is forced to read
data from the external peripheral, and not a copy of initial data held in the cache.) The Cacheable bit can
be configured for both pages and sections.
5.2 IDC Operation
In the ARM processor the cache is searched regardless of the state of the C bit, only reads that miss the
cache are affected.
q Cacheable reads
— C = 1: A line fetch of 4 words is performed and randomly placed in a cache bank.
q Uncacheable reads
— C = 0: An external memory access is performed and the cache is not written.
5.2.1 IDC Validity
The IDC operates with virtual addresses, so ensure that the contents remain consistent with the virtual-
to-physical mappings performed by the MMU. If the memory mappings are changed, the IDC validity must
be ensured.
5.2.2 Software IDC Flush
The entire IDC can be marked as invalid by writing to the ARM processor IDC Flush register (register 7).
The cache is flushed immediately the register is written, but note that the next two instruction fetches may
come from the cache before the register is written.
5.2.3 Doubly-Mapped Space
Since the cache works with virtual addresses, it is assumed that every virtual address maps to a different
physical address. If the same physical location is accessed by more than one virtual address, the cache
cannot maintain consistency, since each virtual address has a separate entry in the cache, and only one
entry is updated on a processor write operation. To avoid any cache inconsistencies, both doubly-mapped
virtual addresses should be marked as uncacheable.
June 1997
ADVANCE DATA BOOK v2.0
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IDC