CL-PS7500FE Datasheet, PDF (57/251 Pages) Cirrus Logic – System-on-a Chip for Internet Appliance

CL-PS7500FE
System-on-a-Chip for Internet Appliance
In all modes, 16 registers (R0 to R15) are directly accessible. All registers except R15 are general-pur-
pose and can be used to hold data or address values. Register R15 holds the PC. When R15 is read, bits
1:0 are ‘0’, and bits 31:2 contain the PC. A seventeenth register, CPSR (Current Program Status register),
is also accessible. It contains condition code flags and the current mode bits and can be thought of as an
extension to the PC.
R14 is used as the subroutine link register and receives a copy of R15 when a Branch and Link instruction
is executed. It can be considered a general-purpose register at all other times. R14_svc, R14_irq,
R14_fiq, R14_abt, and R14_und are used to hold the return values of R15 when interrupts and exceptions
arise, or when Branch and Link instructions are executed within interrupt or exception routines.
FIQ mode has seven banked registers mapped to R8–14 (R8_fiq–R14_fiq). Many FIQ programs do not
need to save any registers.
User mode, IRQ mode, Supervisor mode, Abort mode, and Undefined mode each have two banked reg-
isters mapped to R13 and R14. The two banked registers allow these modes to each have a private stack
pointer and link register.
Supervisor, IRQ, Abort, and Undefined mode programs require more than these two banked registers and
are expected to save some or all of the caller’s registers (R0 to R12) on their respective stacks. They are
then free to use these registers that they restore before returning to the caller.
In addition, there are also five SPSRs (Saved Program Status registers) that are loaded with the CPSR
when an exception occurs. There is one SPSR for each privileged mode.
7.3.1 PSRs (Program Status Registers)
The format of the PSRs is shown in Figure 7-4.
FLAGS
CONTROL
31 30 29 28 27
N
Z
C
V
.
8
7
6
5
4
3
2
1
0
.
.
I
F
. M4 M3 M2 M1 M0
Overflow
Carry / Borrow / Extend
Zero
Negative / Less Than
Figure 7-4. Format of the PSRs
Mode bits
FIQ disable
IRQ disable
7.3.1.1 Condition Code Flags
The N, Z, C, and V bits are the condition code flags. The condition code flags in the CPSR can be changed
as a result of arithmetic and logical operations in the processor and can be tested by all instructions to
determine if the instruction is to be executed.
Interrupt Disable Bits
The I and F bits are the interrupt disable bits. The I bit disables IRQ interrupts when set; the F bit disables
FIQ interrupts when set.
56
REGISTER DESCRIPTIONS
ADVANCE DATA BOOK v2.0
June 1997