CL-PS7500FE Datasheet, PDF (45/251 Pages) Cirrus Logic – System-on-a Chip for Internet Appliance

CL-PS7500FE
System-on-a-Chip for Internet Appliance
VIRTUAL ADDRESS
31
20 19
0
TABLE INDEX
SECTION INDEX
TRANSLATION TABLE BASE
31
14 13
0
TRANSLATION BASE
18
31
14 13
12
21 0
TRANSLATION BASE
TABLE INDEX
00
FIRST LEVEL DESCRIPTOR
31
20 19
12 11 10 9 8
54321 0
SECTION BASE ADDRESS
AP
DOMAIN 1 C B 1 0
12
31
PHYSICAL ADDRESS
20 19
20
0
SECTION BASE ADDRESS
SECTION INDEX
Figure 6-6. Section Translation
Bit Description
2 (B – Bufferable) Indicates that data at this address is written through the WB (if the write buffer is enabled).
3 (C – Cacheable) Indicates that data at this address is placed in the IDC (if the cache is enabled).
11:4 Specify the access permissions (AP[3:0]) for the four subpages and interpretation of these bits is described earlier in
Table 6-1 on page 41.
15:12 For large pages, these bits are programmed as ‘0’.
Bits 31:12 (small pages) or bits 31:16 (large pages) form the corresponding bits of the physical address — the physical page
number. (The page index is derived from the virtual address as illustrated in Figure 6-7 and Figure 6-8.)
6.5 Translating Small Page References
Figure 6-7 illustrates the complete translation sequence for a 4-Kbyte small page. Page translation
involves one additional step beyond that of a section translation: the Level One descriptor is the Page
Table descriptor, and this is used to point to the Level Two descriptor, or Page Table entry. (Note that the
access permissions are now contained in the Level Two descriptor and must be checked before the phys-
ical address is generated. The sequence for checking access permissions is described in Section 6.10.4
on page 50.)
44
ARM PROCESSOR MMU
ADVANCE DATA BOOK v2.0
June 1997