CS4341 Datasheet, PDF (8/36 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
SWITCHING CHARACTERISTICS (T_A = -10 to 70°C; VA = 2.7V - 5.5V; Inputs: Logic 0 = 0V,
Logic 1 = VA, C_L = 20pF)
Parameters
Input Sample Rate
MCLK Pulse Width High
MCLK/LRCK = 512
MCLK Pulse Width Low
MCLK/LRCK = 512
MCLK Pulse Width High MCLK / LRCK = 384 or 192
MCLK Pulse Width Low MCLK / LRCK = 384 or 192
MCLK Pulse Width High MCLK / LRCK = 256 or 128
MCLK Pulse Width Low MCLK / LRCK = 256 or 128
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
MCLK / LRCK = 512, 256 or 384
Symbol
Fs
t_sclkl
t_sclkh
t_sclkw
Min
2
10
10
21
21
31
31
40
20
20
----------1-----------
( 128 )F s
Typ Max Units
-
100
kHz
-
1000
ns
-
1000
ns
-
1000
ns
-
1000
ns
-
1000
ns
-
1000
ns
50
60
%
-
-
ns
-
-
ns
-
-
ns
SCLK Period
MCLK / LRCK = 128 or 192 t_sclkw
(^{---6---4--1--})^--F----s--
-
-
ns
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only)
SCLK Period
SCLK rising to LRCK edge
t_slrd
t_slrs
t_sdlrs
t_sdh
(Note 9)
(Note 10)
t_sclkw
t_sclkr
20
20
20
20
-
-------1---------
SCLK
-
-
-
ns
-
-
ns
-
-
ns
-
-
ns
50
-
%
-
-
ns
t---s---c---l--k---w---
-
µs
2
SDATA valid to SCLK rising setup time
t_sdlrs
----------1----------- + 10
-
-
ns
( 512 ) F s
SCLK rising to SDATA hold time
t_sdh
----------1----------- + 15
-
-
ns
MCLK / LRCK = 512, 256 or 128
( 512 ) F s
SCLK rising to SDATA hold time
t_sdh
----------1----------- + 15
-
-
ns
MCLK / LRCK = 384 or 192
( 384 ) F s
Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50% ±1/2 MCLK Period.
10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK
ratio. (See Figures 20-26)
8
DS298PP2