CS4341 Datasheet, PDF (11/36 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
SWITCHING CHARACTERISTICS - CONTROL PORT
(T_A = 25 °C; VA = +5 V ±5%; Inputs: logic 0 = AGND, logic 1 = VA, C_L = 30 pF)
SPI Mode
Parameter
Symbol
Min
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
f_sclk
-
t_srs
500
(Note 12)
t_spi
500
t_csh
1.0
t_css
20
t_scl
66
t_sch
66
t_dsu
40
(Note 13)
t_dh
15
(Note 14)
t_r2
-
(Note 14)
t_f2
-
Max
Unit
6
MHz
-
ns
-
ns
-
µs
-
ns
-
ns
-
ns
-
ns
-
ns
100
ns
100
ns
Notes: 12. t_spi only needed before first falling edge of CS after RST rising edge. t_spi = 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For F_SCK < 1 MHz
RST
t _srs
CS
t _spi t _css
t _scl t _sch
t _csh
CCLK
t _r2
t _f2
CDIN
t _{dsu t dh}
Figure 5. SPI Control Port Timing
DS298PP2
11