CS4341 Datasheet, PDF (31/36 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
LRCK
SCLK
Left Channel
Right Channel
SDATA 0
23 22 21 20 19 18
76543210
23 22 21 20 19 18
76543210
32 clocks
Internal SCLK Mode
Right Justified, 24-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
External SCLK Mode
Right Justified, 24-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 48 Cycles per LRCK
Period
Figure 23. CS4341 Format 3
LRCK
SCLK
Left Channel
Right Channel
SDATA 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode
Right Justified, 20-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
External SCLK Mode
Right Justified, 20-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 40 Cycles per LRCK
Period
Figure 24. CS4341 Format 4
LRCK
SCLK
Left Channel
Right Channel
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode
Right Justified, 16-Bit DataINT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
External SCLK Mode
Right Justified, 16-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 32 Cycles per LRCK
Period
Figure 25. CS4341 Format 5
DS298PP2
31