CS4341 Datasheet, PDF (16/36 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
4.3 DIGITAL INTERFACE FORMAT
Mode Control Register (address 01h)
7
AMUTE
6
DIF2
5
DIF1
4
DIF0
3
DEM1
2
DEM0
1
POR
0
PDN
Access:
R/W in I²C and write only in SPI.
Default:
0 - Format 0 (I²S, up to 24-bit data, 64 x Fs Internal SCLK)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the
Digital Interface Format and the options are detailed in Figures 20-26.
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
0
1
0
1
0
1
0
1
DESCRIPTION
I²S, up to 24-bit data, 64 x Fs Internal SCLK
I²S, up to 24-bit data, 32 x Fs Internal SCLK
Left Justified, up to 24-bit data
Right Justified, 24-bit Data
Right Justified, 20-bit Data
Right Justified, 16-bit Data
Right Justified, 18-bit Data
Identical to Format 1
Table 3. Digital Interface Formats
FORMAT
0
1
2
3
4
5
6
7
FIGURE
20
21
22
23
24
25
26
20
4.4 DE-EMPHASIS CONTROL
Mode Control Register (address 01h)
7
AMUTE
6
DIF2
5
DIF1
4
DIF0
Access:
R/W in I²C and write only in SPI.
3
DEM1
2
DEM0
1
POR
0
PDN
Default:
0 - Disabled
Function:
Implementation of the standard 15µs/50µs digital de-emphasis filter response, Figure 27, requires re-
configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample
rates. NOTE: De-emphasis is not available in High-Rate Mode.
DEM1
0
0
1
1
DEMO
0
1
0
1
Disabled
44.1kHz
48kHz
32kHz
DESCRIPTION
Table 4. De-emphasis Filter Configurations
16
DS298PP2