CS4341 Datasheet, PDF (3/36 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
Analog Output - AOUTA and AOUTB..................................................................................... 22
Reference Ground - REF_GND.............................................................................................. 22
Positive Voltage Reference - FILT+........................................................................................ 22
Quiescent Voltage - VQ .......................................................................................................... 22
Master Clock - MCLK ............................................................................................................. 23
Left/Right Clock - LRCK ......................................................................................................... 23
Serial Audio Data - SDATA .................................................................................................... 23
Serial Clock - SCLK ................................................................................................................ 24
Reset - RST............................................................................................................................ 24
Serial Control Interface Clock - SCL/CCLK ........................................................................... 24
Serial Control Data I/O - SDA/CDIN ....................................................................................... 24
Address Bit / Chip Select - AD0/CS........................................................................................ 24
Mute Control - MUTEC ........................................................................................................... 24
6. APPLICATIONS ..................................................................................................................... 25
6.1 Grounding and Power Supply Decoupling ....................................................................... 25
6.2 Oversampling Modes ....................................................................................................... 25
6.3 Recommended Power-up Sequence ............................................................................... 25
6.4 Use of the Power ON/OFF Quiescent Voltage Ramp ..................................................... 25
7. CONTROL PORT INTERFACE .............................................................................................. 26
7.1 SPI Mode ......................................................................................................................... 26
7.2 I²C Compatible Mode ...................................................................................................... 26
7.2 Memory Address Pointer (MAP) ....................................................................................... 27
8. PARAMETER DEFINITIONS .................................................................................................. 33
Total Harmonic Distortion + Noise (THD+N) .......................................................................... 33
Dynamic Range ...................................................................................................................... 33
Interchannel Isolation ............................................................................................................. 33
Interchannel Gain Mismatch ................................................................................................... 33
Gain Error ............................................................................................................................... 33
Gain Drift ................................................................................................................................ 33
9. REFERENCES ........................................................................................................................ 33
10. PACKAGE DIMENSIONS .................................................................................................... 34
LIST OF FIGURES
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External Serial Mode Input Timing ................................................................................. 9
Internal Serial Mode Input Timing .................................................................................. 9
Internal Serial Clock Generation .................................................................................... 9
I²C Control Port Timing ................................................................................................ 10
SPI Control Port Timing ............................................................................................... 11
Typical Connection Diagram ........................................................................................ 12
SPI Mode Control Port Formating ................................................................................ 27
I²C Mode Control Port Formating ................................................................................ 27
Base-Rate Stopband Rejection .................................................................................... 28
Base-Rate Transition Band .......................................................................................... 28
Base-Rate Transition Band (Detail) ............................................................................. 28
Base-Rate Passband Ripple ........................................................................................ 28
High-Rate Stopband Rejection .................................................................................... 28
High-Rate Transition Band ........................................................................................... 28
High-Rate Transition Band (Detail) .............................................................................. 29
High-Rate Passband Ripple ......................................................................................... 29
Output Test Load ......................................................................................................... 29
DS298PP2
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