AMC6821 Datasheet, PDF (8/47 Pages) Burr-Brown (TI) – Analog Monitor and Control Circuit

AMC6821
SBAS386A – MAY 2006 – REVISED MAY 2006
www.ti.com
In the write multiple bytes operation, the address pointer of the AMC6821 increments by '1' after the data are
written, until it reaches the last register address (0x3F). If the host continues to transfer data into the AMC6821
after writing the last location, all data are ignored until the operation stops. When reading multiple bytes, the
address pointer of the AMC6821 increments by '1' after transmitting the data until it reaches the last register
address (0x3F). If the host continues clocking data out after reading the last location, the value 0x00 is sent out
until the operation stops.
SMBus ALERT RESPONSE ADDRESS (ARA)
The alert response address is a feature of SMBus devices that allows an interrupting device to identify itself to
the host when multiple devices issue simultaneous interrupts. The SMBALERT pin is an open-drain interrupt
output pin. When the AMC6821 issues an interrupt request, the following procedure occurs:
1. SMBALERT is pulled low.
2. The bus master sends an alert response address or ARA (ARA = 0001100), and initiates a read operation,
as shown in Table 3.
3. The AMC6821 responds to the ARA by sending the slave address back. The 7-bit device slave address is
placed in the seven most significant bits of the byte; the last bit is '0'.
4. The master receives the AMC6821 slave address and starts the interrupt service.
5. If more than one device pulls the SMBus low, the highest priority (lowest slave address) device wins the
communication right via standard arbitration during the slave address transfer (refer to the SMBus
specification version 2.0 for details).
6. To service the interrupt request of the AMC6821, the master must read the status register. Most interrupt
source bits in the status registers are cleared after reading the status register, and are reasserted if the error
condition still exists on the next monitoring cycle. The SMBALERT only clears if the interrupt has been
resolved.
Table 3. ARA Operation
S
ALERT RESPONSE ADDRESS
RD
ACK
DATA
NACK
P
00001100
7-bit MSB: slave address of AMC6821 LSB = 0
S = start condition; P = stop condition; shaded = slave to master; unshaded = master to slave; RD = read (bit value of 1); NACK = not acknowledged.
SMBus TIMEOUT
The AMC6821 has a programmable SMBus timeout function. If the timeout function is enabled (when a single
clock is held low longer than 30ms ±10%), the AMC6821 releases the bus (stops driving the bus and lets SCLK
and SDA float high), resets the communication, and is able to receive new START conditions. If the timeout
function is disabled (when the clock resumes after being held low for longer than 30ms), the AMC6821
continues the bus communication at the current point. To disable the timeout function, set the bit TODIS (bit 7 of
Configuration Register 4) to '1'. To enable this function, clear the bit TODIS to '0'. After power-on or reset,
TODIS is cleared and the timeout function is enabled.
POWER-ON RESET AND START OPERATION
After power-on, all registers are set to the power-on default values. The device does not perform any monitoring
functions until the START bit of Configuration Register 1 is set ('1'). No detections are executed until the first
monitoring cycle is completed, and all measurement data registers (such as remote and local temp-data
registers and the TACH data register) are updated with the new measured value. No interrupt signals are
generated until the first cycle of monitoring and detection is completed. This process avoids any false alarms
caused by the power-on default setting.
After power-on, the fan spin-up process is performed. At the end of spin-up, the duty cycle of the PWM driver is
adjusted to 33%. (Refer to the Fan Spin-Up section for details). Device status after software reset is similar to
power-on reset.
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