AMC6821 Datasheet, PDF (11/47 Pages) Burr-Brown (TI) – Analog Monitor and Control Circuit

AMC6821
www.ti.com
SBAS386A – MAY 2006 – REVISED MAY 2006
APPLICATION INFORMATION (continued)
Table 4. Temperature Data Format
TEMPERATURE (°C)
+127
+125
+100
+75
+50
+25
+10
+1
0
–1
–25
–50
–75
–100
–125
–128
BINARY DIGITAL CODE (11 bits)
01111111000
01111101000
01100100000
01001011000
00110010000
00011001000
00001010000
00000001000
00000000000
11111111000
11100111000
11001110000
10110101000
10011100000
10000011000
10000000000
Temperature Out-of-Range Detection
The AMC6821 has the following temperature limitation detections:
1. High and Low Temperature Limit: The value of the High-Temp-Limit and Low-Temp-Limit registers specify
the remote or local temperature ranges of normal operation. When the local or remote temperatures are
equal to or above the value of the corresponding High-Temp-Limit register, the LTH or RTH bits in the status
register are set ('1'). Likewise, when the local or remote temperatures are less than or equal to the
corresponding Low-Temp-Limit register, the LTL or RTL bits in the status register are set ('1').
When the local temperature is out-of-range (LTH = 1 or LTL = 1), the local temperature out-of-range event
occurs. The LTO bit in the status register is set ('1'), and the LTO interrupt is generated via the SMBALERT
pin if it is enabled (the LTOIE bit of Configuration Register 2 is set). Similarly, when the remote temperature
is-out-of range (RTH = 1 or RTL = 1), the remote temperature out-of-range event occurs. The RTO bit in the
status register is set ('1'), and the RTO interrupt is generated via the SMBALERT pin if it is enabled (the
RTOIE bit of Configuration Register 2 is set).
2. Critical Limit: Critical temperature limit is the highest allowed temperature of remote or local temperature.
When the temperature is greater than or equal to the corresponding critical temperature, the LTCT or RTCT
bit of the status register is set ('1'), the output of the OVR pin goes low, and a non-maskable interrupt is
generated through the SMBALERT pin (low).
3. Passive Cooling Temperature (PSV) Limit: This limit defines the threshold of the passive cooling. In the
auto temperature fan control mode, the system enters a passive cooling condition when the active control
temperature is equal to or below this limit, and the fan stops. In passive cooling, the LPSV bit of Status
Register 2 (0x03) is set ('1'), and a PSV interrupt is generated on the SMBALERT pin if enabled (PSVIE =
1). Note that reading the Status Register clears the LPSV bit. After reading, if the active control temperature
remains equal to or below the PSV temperature, this bit reasserts on next monitoring cycle.
4. THERM Limit: This limit is an additional fail-safe threshold. When the local or remote temperature is equal
to or above this limit, the corresponding L-THERM or R-THERM bit is set ('1'), and the THERM pin is
asserted low, which can be used to throttle the CPU clock. Furthermore, the THERM interrupt is generated
on the SMBALERT pin if enabled (THERMOVIE = 1). Reading the Status Register 1 clears the R-THERM
and L-THERM bits. Once cleared, these bits are not reasserted until the temperature falls 5°C below the
THERM limit, even if the THERM condition persists. If the THERM-FAN-EN bit of the Configuration Register
3 is set ('1'), L-THERM = 1 or R-THERM = 1 forces the fan to run at full-speed. When THERM-FAN-EN = 0,
the status of the L-THERM and R-THERM bits do not affect the fan speed directly. Note that the THERM
limit can be lower or higher than other temperature limits. For example, if the THERM limit is lower than the
PSV temperature limit, then the CPU clock can be throttled while the cooling fan is off.
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