AMC6821 Datasheet, PDF (24/47 Pages) Burr-Brown (TI) – Analog Monitor and Control Circuit

AMC6821
SBAS386A – MAY 2006 – REVISED MAY 2006
www.ti.com
The bits [R-TEMP4:R-TEMP0] of the Remote TEMP-FAN Control Register and the bits [L-TEMP4:L-TEMP0] of
the Local TEMP-FAN Control Register are the low temperature bits that define the low temperature of the control
loops. Bits [SPL2:SPL0] of these registers are the slope bits that define the increment of the duty cycle when the
temprature increases 1°C. The bits [RATE2:RATE0] of the DCY-RAMP Register (bits [4:1], 0x23) specify the
updating rate of the duty cycle in the temp-fan control mode, and the bits [STEP1:STEP0] define how much the
duty cycle is adjusted by each updating. The high temperature can be calculated by Equation 3:
High
Temperature
+
(Low
Temperature)
)
(100
*
Value
of
DCY−LOW−TEMP
Slope
Register)
(3)
100%
Temperature-to-DCY Adjustment Range
DCY-LOW-TEMP
(DCY at Low Temperature,
Default is 33%)
DCY increases when the temperature rises.
DCY decreases when the temperature reduces.
RPM = 0
0%
Low-Temp-Limit
LOW-TEMP (Low Temperature)
PSV-Temp
(Passive Cooling Temperature)
Out-of-Range
Actual Temperature
Normal Range
Out-of-Range
Figure 19. Active Control Temperature—PWM Duty Cycle
When the active control temperature is equal to or below the corresponding low temperature, the duty cycle is
equal to the value of the DCY-LOW-TEMP Register and the fan runs at a predefined minimum speed. When the
control temperature is equal to or higher than the corresponding high temperature, the PWM duty cycle is set to
100% and the fan runs at full-speed. When the active control temperature is equal to or below the corresponding
value of the PSV-Temp Register (the predefined passive cooling temperature), the fan stops and the PWM duty
cycle is set to 0.
When the actual duty cycle is different from the desired value, the duty cycle is adjusted automatically. When the
RAMPE bit of the DCY-RAMP Register is cleared ('0'), the duty cycle changes to the desired value immediately
after being calculated. When the RAMPE bit is '1', the duty cycle changes to the new value gradually.
The DCY-RAMP Register specifies how quickly the duty cycle changes. The duty cycle can be checked every
0.0625 of a second to every eight seconds, depending on the bits [RATE2:RATE0] bits. It changes
1/255(0.392%) to 4/255 (1.57%) each time, depending on the bits [STEP1:STEP0] bits. When the difference
between the actual value and the desired value is equal to or less than the adjustment threshold (as defined by
the bits [THRE1:THRE0] bits), the adjustment finishes. See the DCY-RAMP Register for details. When the
TACH monitoring is enabled (TACH-EN bit, bit 2 of 0x02, is set to '1') and the TACH-MODE bit (bit 1 of 0x02) is
cleared ('0'), the duty cycle is forced to 0% when the calculated value is less than 7%. If the TACH monitoring is
disabled (TACH-EN = 0) or the TACH-MODE bit is set ('1'), the duty cycle is always set to the calculated value
even if the value is less than 7%.
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