CS42L50 Datasheet, PDF (41/48 Pages) Cirrus Logic – Low Voltage, Stereo CODEC with headphone Amp

CS42L50
LRCK
SCLK
SDATA
LRCK
SCLK
SDATA
Left Channel
Right Channel
M SB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LS B
M SB -1 -2 -3 -4 +5 +4 +3 +2 +1 LS B
Left Justified, up to 24-Bit Data. Data Valid on Rising
Edge of SCLK.
Figure 25. Left Justified, up to 24-bit data
Left Channel
Right Channel
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 cRloicgksht Justified, 16-Bit Data. Data Valid on Rising Edge of
SCLK. SCLK Must Have at Least 32 Cycles per LRCK
Period.
Figure 26. Right Justified, 16-bit data
LRCK
SCLK
SDATA 0
Left Channel
Right Channel
23 22 21 20 19 18
76543210
23 22 21 20 19 18
32 clo_Rck_is_{ght Justified, 24-Bit Data. Data Valid on Rising Edge of}
SCLK. SCLK Must Have at Least 48 Cycles per LRCK
Period.
Figure 27. Right Justified, 24-bit data
76543210
DS544PP1
41