CS42L50 Datasheet, PDF (32/48 Pages) Cirrus Logic – Low Voltage, Stereo CODEC with headphone Amp

CS42L50
Analog
Input/Output
AIN_Rx
AIN_Lx
4, 5, Analog Inputs (Input) - The full scale analog input level is specified in the Analog Input Characteristics
7,8 ^{specification table.}
AOUTL
AOUTR
15, Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Output Char-
16 ^{acteristics specifications table.}
HP_A
HP_B
12, Headphone Outputs (Output) - The full scale analog headphone output level is specified in the Analog
14 ^{Output Characteristics specifications table.}
Control Port
Interface
SCL
27 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up
resistor to the logic interface voltage as shown in the Typical Connection Diagram.
SDA
26 Serial Control Data (Input/Output) - SDA is a data I/O line and requires an external pull-up resistor to
the logic interface voltage, as shown in the Typical Connection Diagram.
Control & Misc.
AFLTR
AFLTL
1,2 Anti-Aliasing Capacitors (Output) - Anti-aliasing capacitors for the left and right channels. An external
capacitor is required from AFLTR and AFLTL to ground, as shown in the Typical Connections Diagram.
AFLTR and AFLTL are not intended to supply external current, and any current drawn from these pins
will alter device performance.
FILT+_ADC
3 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Requires the capacitive decoupling to AGND as shown in the Typical Connection Diagram.
FILT+_DAC 10 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Requires the capacitive decoupling to AGND as shown in the Typical Connection Diagram.
MUTEC
17 Mute Control (Output) - The Mute Control pin goes low during power-up initialization, reset, muting,
power-down or if the master clock to left/right clock frequency ratio is incorrect. This pin is intended to be
used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single
supply system. The use of an external mute circuit is not mandatory but may be desired for designs
requiring the absolute minimum in extraneous clicks and pops.
RST
28 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low. When high, the control port becomes operational and the CP_EN bits must be set and
the PDN bits must be cleared before normal operation will occur. The control port cannot be accessed
when Reset is low.
32
DS544PP1