CS42L50 Datasheet, PDF (14/48 Pages) Cirrus Logic – Low Voltage, Stereo CODEC with headphone Amp

CS42L50
SWITCHING CHARACTERISTICS - CONTROL PORT
(T_A = 25° C; VL = 1.7 V - 3.3 V; Inputs: logic 0 = GND, logic 1 = VL, C_L = 30 pF)
Parameter
Symbol
Min
SCL Clock Frequency
f_scl
-
RST Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 17)
t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of SCL
t_rc
-
Fall Time of SCL
t_fc
-
Rise Time of SDA
t_rd
-
Fall Time of SDA
t_fd
-
Setup Time for Stop Condition
t_susp
4.7
Max
Unit
100
KHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
25
ns
25
ns
1
µs
300
ns
-
µs
Note: 17. Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
RST
t _irs
Stop
S ta rt
R epeated
S ta rt
SDA
t _buf
t _hdst
t _high
t _hdst
tf
SCL
t _low t _hdd
t _sud
t _sust
tr
Figure 3. Control Port Timing - I²C^â
Stop
t _susp
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DS544PP1