CS42L50 Datasheet, PDF (33/48 Pages) Cirrus Logic – Low Voltage, Stereo CODEC with headphone Amp

CS42L50
6. APPLICATIONS
6.1 Grounding and Power Supply
Decoupling
As with any high resolution converter, the
CS42L50 requires careful attention to power sup-
ply and grounding arrangements to optimize per-
formance. Figure 4 shows the recommended power
arrangement with VA, VA_HP, and VL connected
to clean supplies. Decoupling capacitors should be
located as close to the device package as possible.
If desired, all supply pins may be connected to the
same supply, but a decoupling capacitor should still
be used on each supply pin.
6.2 Clock Modes
The CS42L50 operates in one of two clocking
modes. Single Speed Mode supports input sample
rates up to 50 kHz, and Double Speed Mode sup-
ports input sample rates up to 100 kHz. All clock
modes use 64x oversampling.
6.3 EP73xx Serial Port Interface
Special considerations must be made when inter-
facing the CS42L50 with the EP73xx series of
ARM processors. To receive stereo data from the
ADC, connect the MCLK pin (pin 19) of the
CS42L50 to the BUZ pin (pin 93) of the EP73xx,
and run the serial port in 64Fs mode with MCLK
generation enabled on the EP73xx. Any other con-
figuration, either hardware or software modes, will
result in mono data being produced from the ADC
of the CS42L50.
6.4 De-Emphasis
The CS42L50 includes on-chip digital de-empha-
sis. Figure 31 shows the de-emphasis curve. The
frequency response of the de-emphasis curve will
scale proportionally with changes in sample rate,
Fs.
The de-emphasis feature is included to accommo-
date older audio recordings that utilize pre-empha-
sis equalization as a means of noise reduction.
6.5 Recommended Power-up Sequence
1) Hold RST low until the power supply, master
clock and left/right clock are stable. In this
state, the control port is reset to its default set-
tings and VQ_ADC and VQ_DAC will remain
low.
2) Bring RST high. The device will remain in a
low power state and VQ_ADC and VQ_DAC
remain low. The control port will be accessible
at this time and the desired register settings can
be loaded after setting the CP_EN bits and
while keeping the PDN bits set to 1.
3) Once the registers are configured as desired, set
the PDN bits to 0, initiating the power-up se-
quence.
6.6 Optional External Headphone Mute
An external headphone mute circuit, as shown in
the CDB42L50 datasheet schematic, is recom-
mended to minimize the effects of output transients
during power-up and power-down. This technique
minimizes the audio transients commonly pro-
duced by single-ended, single-supply converters
when it is implemented with external DC-blocking
capacitors connected in series with the audio out-
puts.
Use of the Mute Control function on the line out-
puts is recommended for designs requiring the ab-
solute minimum in extraneous clicks and pops.
Also, use of the Mute Control function can enable
the system designer to achieve idle channel
noise/signal-to-noise ratios only limited by the ex-
ternal mute circuit. See the CDB42L50 datasheet
for a suggested mute circuit.
7. CONTROL PORT INTERFACE
The control port is used to load all the internal set-
tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if
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