CS42L50 Datasheet, PDF (3/48 Pages) Cirrus Logic – Low Voltage, Stereo CODEC with headphone Amp

CS42L50
4.2.5 Power Down Line Amplifier (PDNLN) ............................................................................ 24
4.2.6 Power Down (PDN) ....................................................................................................... 24
4.2.7 Control Port Enable (CP_EN) ........................................................................................ 24
4.2.8 Channel A Analog Headphone Attenuation Control (address 02h) (HVOLA) .............. 25
4.2.9 Channel B Analog Headphone Attenuation Control (address 03h) (HVOLB) .............. 25
4.2.10 Channel A Digital Volume Control (address 04h) (DVOLA) ....................................... 25
4.2.11 Channel B Digital Volume Control (address 05h) (DVOLB) ....................................... 25
4.2.12 Tone Control (address 06h)........................................................................................ 26
4.2.13 Bass Boost Level (BB)................................................................................................. 26
4.2.14 Treble Boost Level (TB)............................................................................................... 26
4.2.15 Mode Control (address 07h)....................................................................................... 27
4.2.16 Bass Boost Corner Frequency (BBCF) ....................................................................... 27
4.2.17 Treble Boost Corner Frequency (TBCF) ..................................................................... 27
4.2.18 Channel A Volume = Channel B Volume (A=B) .......................................................... 27
4.2.19 De-Emphasis Control (DEM) ....................................................................................... 28
4.2.20 Digital Volume Control Bypass (VCBYP) .................................................................... 28
4.2.21 Volume and Mixing Control (address 0Ah)................................................................. 28
4.2.22 Tone Control Mode (TC).............................................................................................. 28
4.2.23 Tone Control Enable (TC_EN) .................................................................................... 28
4.2.24 ATAPI Channel Mixing and Muting (ATAPI)................................................................ 29
4.2.25 Mode Control 2 (address 0Bh) ................................................................................... 29
4.2.26 Master Clock Divide Enable (MCLKDIV) ..................................................................... 29
4.2.27 Line Amplifier Gain Compensation (LINE)................................................................... 29
4.2.28 Digital Interface Format (DIF) ...................................................................................... 30
5. PIN DESCRIPTIONS ............................................................................................................... 31
6. APPLICATIONS ...................................................................................................................... 33
6.1 Grounding and Power Supply Decoupling ....................................................................... 33
6.2 Clock Modes .................................................................................................................... 33
6.3 EP73xx Serial Port Interface ........................................................................................... 33
6.4 De-Emphasis ................................................................................................................... 33
6.5 Recommended Power-up Sequence ............................................................................... 33
6.6 Optional External Headphone Mute ................................................................................ 33
7. CONTROL PORT INTERFACE ............................................................................................... 33
7.1 Memory Address Pointer (MAP) ...................................................................................... 35
7.2 INCR (Auto Map Increment Enable) ................................................................................. 35
7.3 MAP0-3 (Memory Address Pointer).................................................................................. 35
8. PARAMETER DEFINITIONS ................................................................................................... 44
9. REFERENCES ......................................................................................................................... 44
10. PACKAGE DIMENSIONS ..................................................................................................... 45
LIST OF FIGURES
Figure 1. SCLK to LRCK and SDIN, Slave Mode .................................................... 13
Figure 2. SCLK to LRCK and SDIN, Master Mode .................................................. 13
Figure 3. Control Port Timing - I²C‚ ......................................................................... 14
Figure 4. CS42L50 Typical Connection Diagram .................................................... 15
Figure 5. Control Port Timing .................................................................................. 35
Figure 6. Decimation Filter Single Speed Stopband Rejection ............................... 36
Figure 7. Decimation Filter Single Speed Transition Band ...................................... 36
Figure 8. Decimation Filter Single Speed Transition Band (Detail) ......................... 36
Figure 9. Decimation Filter Single Speed Passband Ripple ................................... 36
Figure 10.Decimation Filter Double Speed Stopband Rejection .............................. 36
Figure 11.Decimation Filter Double Speed Transition Band .................................... 36
Figure 12.Decimation Filter Double Speed Transition Band (Detail) ........................ 37
DS544PP1
3