CS89712 Datasheet, PDF (40/170 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH 10BASE-T ETHERNET CONTROLLER

CS89712
0x7 or 0x8, as these are the locations for the on-
chip Boot ROM and internal registers.
During Snooze State, the shift clock (CL2), FRM,
and line (CL1) signals are on for the entire display.
The SNZDISP register is used to disable the data
path through the LCD controller after the required
data has been displayed, to save further power. Af-
ter the word address stored in the SNZDISP regis-
ter is reached, the data output pins DD[3:0] will be
blanked to 0 or 1 as defined by the SNZPOL bit,
which is at Bit 10 of the SYSCON2 register. Sec-
tions of the SRAM not used for the display data in
Snooze State can be used for other data storage.
In Snooze State, the LCD controller (if enabled via
the LCDEN bit in the SYSCON1 register) will au-
tomatically fetch data from the on-chip SRAM in
1-bit-per-pixel mode. Before entering Snooze
State, the required display buffer must be trans-
ferred into the on-chip SRAM in a 1-bit-per-pixel
format. On entry to Snooze State, the video frame
size field is reinterpreted for 1-bit-per-pixel data,
and the grey scale mode bits are ignored.
On exit from Snooze State, the CS89712 enters the
Doze State. In Doze State, all of the CS89712, ex-
cept the LCD controller, is operating normally.
The DRAM is taken out of self-refresh and normal
CAS before RAS (CBR) refreshes start. The CPU
is active and takes interrupts at normal speed. In
Doze State, display data continues to be fetched
from the OCSR, as for the Snooze State. DMA for
the display is active only while the number of lines
programmed into the SNZDISP register are dis-
played and DMA/CPU arbitration is carried out
during this time. For the rest of the time, the LCD
controller displays “pixel fill” data on the LCD.
During the Doze State, if some of the OCSR mem-
ory space is not being used to store the video buffer,
the remaining section can be used by the CPU for
general purpose data storage. The remaining sec-
tion is fully address decoded.
Note: The only way to enter the Doze State is by exit
from the Snooze State. Also, the Snooze State
cannot exit directly to the Operating State; it
must go through the Doze State first.
In an application, the CS89712 would spend most
of its time in snooze mode. On interrupt or wake-
up, it moves into Doze State. At this point the OS
identifies the cause of the interrupt and decides
whether it can stay in Doze State (e.g., update a
clock on the display) or if it is woken up because
the user wants to perform a function requiring the
full display. In the latter case, the OS will set the
LCDSNZE bit low and the CS89712 will switch to
the Operating State. In the Operating State, the dis-
play will be automatically switched to the main
frame buffer on the next frame sync. The full LCD
controller is used and data fetched from the buffer
pointed to by the FBADDR register (if LCDSNZE
is low). To ensure correct synchronization it is not
possible to program the LCDSNZE bit to high with
software, this is done automatically as part of the
process of entering the Snooze State. It can, how-
ever, be set low from software. This is how the dis-
play is changed back to the main display after exit
from the Snooze State, if this is required.
It is likely that system software would normally
wake up from the Snooze State for two reasons: 1)
to perform minor OS functions like updating a time
display or polling the keyboard, and 2) to wake up
completely because the user has pressed a key. In
the former case, the LCDSNZE bit would be left
high and the Snooze State re-entered by writing to
the SNOOZE location in the normal way. The chip
would continue to output data from the on-chip
SRAM throughout (which could have been updated
while out of Snooze State). In the second case,
software should write to the LCDSNZE location
soon after exiting from Snooze State. Then the
LCD controller will be re-enabled and the display
cleanly switched across to the main frame buffer as
pointed to by the address in the FBADDR register.
The screen is mapped to the video frame buffer as
one contiguous block where each horizontal line of
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