CS89712 Datasheet, PDF(122/170 Page) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH 10BASE-T ETHERNET CONTROLLER

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CS89712 Datasheet, PDF (122/170 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH 10BASE-T ETHERNET CONTROLLER

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CS89712

3.18.7 Transmit Command Status register (TxCMD, address offset 108h)

7:6

5:0

TxStart

001001

TxPadDis

InhibitCRC

Onecoll

Force

This register contains the latest transmit command which describes how the next packet should be sent. The com-

mand must be written to Ethernet Port offset 0144h in order to initiate a transmission. The software can read the

command from this register (offset 0108h). See Section 2.34, âTransmit Operationâ.

Bit

5:0

7:6

Description

001001: These bits provide an internal address used by the CS89712 to identify this as register

9, the Transmit Command Register. When reading this register, these bits will be 001001, where

the LSB corresponds to Bit 0.

TxStart: This pair of bits determines how many bytes are transferred to the CS89712 before the

MAC starts the packet transmit process.

Bit 7 Bit 6

Start transmission after 5 bytes are in the CS89712

Start transmission after 381 bytes are in the CS89712

Start transmission after 1021 bytes are in the CS89712

Start transmission after the entire frame is in the CS89712

Force: When set in conjunction with a new transmit command, any transmit frames waiting in

the transmit buffer are deleted. If a previous packet has started transmission, that packet is ter-

minated within 64 bit times with a bad CRC.

Onecoll: When this bit is set, any transmission will be terminated after only one collision. When

clear, the CS89712 allows up to 16 normal collisions before terminating the transmission.

InhibitCRC: When set, the CRC is not appended to the transmission.

TxPadDis: When TxPadDis is clear, if the software gives a transmit length less than 60 bytes

and InhibitCRC is set, then the CS89712 pads to 60 bytes. If the software gives a transmit length

less than 60 bytes and InhibitCRC is clear, then the CS89712 pads to 60 bytes and appends the

CRC.

When TxPadDis is set, the CS89712 allows the transmission of runt frames (a frame less than

64 bytes). If InhibitCRC is clear, the CS89712 appends the CRC. If InhibitCRC is set, the

CS89712 does not append the CRC

Table 72. Transmit Command Status

After reset, if no EEPROM is found by the CS89712, then the register has the following initial state. If an EEPROM

is found, then the registerâs initial value may be set by the EEPROM. See Section 2.24, âProgramming the EE-

PROMâ.

Regster value is: 0000 0000 0000 1001

Note: The CS89712 does not transmit a frame if TxLength < 3

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DS502PP2

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