CS89712 Datasheet, PDF (10/170 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH 10BASE-T ETHERNET CONTROLLER

CS89712
When both KBWEN and INTMR2 bit 0 are low,
the device can be awakened only by the external
WAKEUP pin or another enabled interrupt source.
The keyboard interrupt capability allows use of a
polled and/or interrupt-driven keyboard routine.
Notes:The keyboard interrupt is NOT deglitched.
2.2.4 Ethernet Port Software Suspend
The Ethernet port power features work in a differ-
ent manner than detailed above. Suspend mode-
may be entered via software. During this mode, all
internal Ethernet circuits are shut off except the I/O
Base Address register (Ethernet Port offset address
0020h) and the SelfCTL register.
To enter Suspend mode, the SWSuspend bit (Self-
CTL Register, bit 8) is set. To exit SW Suspend,
software must write to the CS89712 Ethernet (used
only to wake the Ethernet port, the Write data is ig-
nored). Upon exit, the CS89712 Ethernet performs
a complete reset, and then goes through a normal
initialization procedure.
2.3 Power-Up Sequence
The following sequence should be followed to en-
sure proper start up. If any of the timing sequences
recommended below are violated, then the part
may not start up properly, requiring a hard reset to
recover.
1) Upon power, the signal nPOR must be held ac-
tive (LOW) for a minimum of 100us, after V_DD
has become settled.
2) After nPOR goes HIGH, the CS89712 will en-
ter the Standby State (and only this state). In
this state, the PLL and CPU are not enabled.
The only method that can be used to allow the
CS89712 to exit the Standby State into the Op-
erating State is by the WAKEUP signal going
active (HIGH).
Note:
It is not a requirement to use the nURESET
signal. If not used, the nURESET signal
must be HIGH, and it must have gone
HIGH prior to nPOR going HIGH. This is
due to the fact that nURESET is latched
into the device by the rising edge of nPOR.
When nURESET is LOW on the rising edge
of nPOR, it can force the device into one of
its Test Mode states.
3) After nPOR goes HIGH, the WAKEUP signal
cannot be detected as going HIGH, until after at
least two seconds. After two seconds, the
WAKEUP signal can become active, and it
must be HIGH for at least 125 us.
4) Before the WAKEUP signal is detected inter-
nally, it must go through a deglitching circuit.
This is why is must be active for at least 125us.
Then the PLL gets enabled. WAKEUP is ig-
nored immediately after waking up the system.
It also ignores it while in the Idle or Operating
State. It can constantly toggle with no affect on
the device. It will only be read again if nPOR
goes low and then high again, or if software has
forced the device back into the Standby State.
5) A maximum of 250 msec will pass before the
CPU starts to fetch the first instruction.
2.4 Resets
There are three asynchronous resets to the
CS89712: nPOR (Power On Reset), nPWRFL, and
nURESET. If any of these are active, a system reset
is generated internally. This will reset all internal
registers in the CS89712 except the RTC data and
match registers. These registers are only cleared by
nPOR allowing the system time to be preserved
through a user reset or power fail condition.
NOTE: The Ethernet Port has different reset conditions
and considerations than described in this sec-
tion. Refer to the following section for resetting
the Ethernet Port.
Any reset will also reset the CPU and cause it to
start execution at the reset vector when the
CS89712 returns to the Operating State.
Three signals are used to internally reset storage el-
ements. These are nPOR, nSYSRES (System Re-
set) and nSTBY. nPOR is an external signal.
nSTBY is equivalent to the external RUN signal.
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